How can I initialize RAM?

[Øyvind Harboe]

I've been scratching my head trying to figure out how I can initialize inferred RAM.

Is there a way I could pass in the initialization vector as a blackbox parameter and write some magic Verilog incantation that both Xilinx will infer and Verilator will understand?

The best I've been able to come up with is pretty arcane and brittle and brittle. It's brittle because when I write out the .txt file that readmemh reads in, then Xilinx tools are finicky about what directory I put that .txt file into. Below  Helper.bankString is a function that writes out the .txt file and returns the name of that .txt file. 

Here's my InitializedBank.v resource for my BlackBox.

/**

 * This is an initialized bank in a syntax that both Xilinx and Verilator undrestands.

 *

 * Ideally we'd be able to pass in the ram initialization data as a parameter, so that we didn't

 * need the bank.txt files.

 *

 * TODO make number of address lines a parameter

 */

module InitializedBank(

  input         clock,

  input         reset,

  input  [15:0] bank_In,

  output [15:0] bank_Out,

  input         bank_ReadEna,

  input  [13:0] bank_ReadRow,

  input         bank_WriteEna,

  input  [13:0] bank_WriteRow

);

  reg [15:0] ram [0:16383];

  reg [15:0] out;

  assign bank_Out = out;

  parameter INITIAL_VALUE = "bank1.txt";

  integer initvar;

  initial $readmemh(INITIAL_VALUE, ram, 0, 16383);

  always @(posedge clock) begin

    if (bank_WriteEna) begin

      ram[bank_WriteRow] <= bank_In;

    end

    if (bank_ReadEna) begin

      out <= ram[bank_ReadRow];

    end

  end

endmodule

class InitializedBank(rows : Int, initial : Array[Byte], bankNum : Int)

 extends BlackBox(Map("INITIAL_VALUE" -> Helper.bankString(rows, initial, bankNum))) with HasBlackBoxResource

{

  val io = IO(new Bundle()

  {

    val clock = Input(Clock())

    val reset = Input(Bool())

    val bank = new BankBundle(rows)

  })

  setResource("/InitializedBank.v")

}

[ch...@berkeley.edu]

I am working on a way of doing it using chisel annotations combined with verilog module binding.  I am out of town for a bit, so I won't have anything for a week or two, but 

I think it is doable.

-chick