asTypeOf on the left hand side?

[Martin Schoeberl]

Hi all,

I have a configurable port, depending on Boolean s4noc:

if (s4noc) {
  val e = rv.tx.bits.asTypeOf(Entry(UInt(32.W)))
  e.data := cp.wrData
  e.time := txDestReg
  cp.rdData := rv.rx.bits.asTypeOf(Entry(UInt(32.W))).data
} else {
  rv.tx.bits := cp.wrData
  cp.rdData := rv.rx.bits
}

If s4noc is false everything compiles and runs fine. However, if s4noc is true, Chisel complains about uninitialized fields:

[info]   firrtl.passes.PassExceptions: firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module CpuInterfaceRV]  Reference rv is not fully initialized.

[info]    : rv.tx.bits.time <= VOID

[info] firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module CpuInterfaceRV]  Reference rv is not fully initialized.

[info]    : rv.tx.bits.data <= VOID

Is the above val e (as an Entry type) not usable on the LHS of an assignment?

Cheers,

Martin

[Albert Magyar]

asTypeOf(X) returns a new wire of type X, so this is working as intended. To complete the code you would need rx.tx.bits := e.asTypeOf(rx.tx.bits)

From the Scala perspective, Chisel asTypeOf is a conversion that returns a new value rather than a cast. It’s generally only possible to implement cast semantics if the source type already has an “is a” relationship with the destination type. Since a Bits isn’t a Bundle, it can’t be a cast-like operator. The other alternative to allow an “assignable asTypeOf” result would be for it to return a type with another layer of indirection that reused the “storage” (actual net allocation) of the wire. However, this “DataRef” would be baked into the basic chisel API; currently, the Chisel core API is rather small, so adding the family of types to support this would probably be too confusing.

I see that the documentation for asTypeOf describes it as a reinterpret cast, so it seems like the docs imply to some extent that what you wrote should work. I think that might just be an example of it being difficult to document both the RTL and Scala semantics of Chisel APIs without being too complex, but it might not be the best analogy.

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