I am trying to pipe-flush the Chisel front-end flow.
Taken the existing ALU block and generated the Chisel/Scala code and the corresponding scala TB and test structure (both files are attached).
Added the annotation in the TB to generate the Verilator back-end. This then generates the Verilator related code, SV & C++ model for the Alu block.
I then try to compile the SV code for the block, plus the C++ model with verilator as follows:
verilator -Wall --cc Kirin_Alu.sv --exe --build Kirin_Alu-harness.cpp
However, the first problem i am encountering is that the Kirin_alu-harness.cpp generated file is making use of undefined class. The VerilatedCov:: class is being referenced but is not defined anywhere.
Is this a Chisel/Sbt bug?
I am using the following:
Verilator 4.034 2020-05-03 rev v4.034
scalaVersion := "2.12.13"
val chiselVersion = "3.5.4"
Thanks in advance