1. The only major requirement is willingness to learn a new language (Chisel and basic Scala) and, installed on your machine: java and a C++ compiler (gcc preferred). As Chisel is an internally hosted domain-specific language/library in Scala, all of your hardware generators/descriptions will essentially be Scala programs. Scala is very closely related to Java (and in fact run using the Java VM).
2. This readme should handle your getting started issues:
https://github.com/ucb-bar/chisel/blob/master/README.md . Note that you need to have a C++ compiler (Chisel assumes this is g++) and java installed on the machine
3. See 2.
4. Running a compiled Chisel program with the flag --backend v will emit a Verilog file, which you are then free to use however you need.
PS: Note that, if you try to use the Chisel tester with the Verilog backend enabled, Chisel will use VCS to compile the Verilog. If you do not have VCS installed, stay to using the C++ backend when using the Chisel tester. Then, use Modelsim or some other Verilog compiler/testing suite to test generated Verilog with your own Verilog testbenches. Regardless, you can still generate Verilog without VCS installed (you just may find it hard to test!).