Chisel v3.6.0-RC2 - chiseltest doesn't use LLVM CIRCT

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Øyvind Harboe

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Mar 14, 2023, 8:51:30 AM3/14/23
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I looked at the generated Verilog for chiseltest test-cases and it doesn't use LLVM CIRCT.

Is there a way to enable LLVM CIRCT in chiseltest?

Kevin Laeufer

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Mar 14, 2023, 12:11:14 PM3/14/23
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Hi Øyvind,

chiseltest will stick with the original `firrtl` compiler since CIRCT
lacks support for certain compiler passes and backends that are needed
for the full chiseltest functionality. Since we have a firrtl spec that
both CIRCT and firrtl try to comply with, using CIRCT for tapeout and
firrtl for testing shouldn't be a big problem for now. If you think
about it, VCS is also using a different Verilog implementation than the
Vivado synthesis tool or Design Compiler.

The SiFive guys are working on a `chiseltest` alternative that will
feature CIRCT support, not sure what the current status on that is.

Best,
Kevin
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Øyvind Harboe

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Mar 14, 2023, 1:37:38 PM3/14/23
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Thanks!

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