Chisel v3.6.0-RC2 has been released!

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Jack Koenig

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Feb 28, 2023, 12:23:50 AM2/28/23
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Howdy Chiselers,

I am very delighted to announce that we have released v3.6.0-RC2 of the various Chisel-related projects:


Treadle and FIRRTL also have 1.6.0-RC2 releases but with relatively minor changes.

The 3.6 release is a big step for the future of Chisel as it is the transitional release from the original Scala FIRRTL Compiler to the new LLVM MLIR-based FIRRTL Compiler. Please see the Chisel release notes linked above.

Please try out Chisel v3.6.0-RC2 to help us squash any bugs before the final v3.6.0 release!

~Jack on behalf of the Chisel development team

P.S. My usual Scastie template now using 3.6.0-RC2: https://scastie.scala-lang.org/9pywNJBbQ4e1Dp5bo4rpNg

Øyvind Harboe

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Mar 13, 2023, 7:43:22 AM3/13/23
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Notes from upgrading.

Got some nice new warnings about bit widths and shifts. 

Some things I had to change to get BoringUtils.bore() to work:

-  val snoopAsUInt = snoop.asUInt
+  val snoopAsUInt = WireInit(snoop.asUInt)

Another example:

-  val foo = VecInit(xxx.map(_.yyy)).count(a => a)
-  val bar = VecInit(xxx.map(_.yyy)).reduce(_ +& _)
+ val foo = WireInit(VecInit(xxx.map(_.yyy)).count(a => a))
+ val bar = WireInit(VecInit(xxx.map(_.yyy)).reduce(_ +& _))

Need to complete this change before I can try out P&R: https://github.com/chipsalliance/chisel/issues/3031#issuecomment-1439326320


Øyvind Harboe

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Mar 13, 2023, 3:20:54 PM3/13/23
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One more problem. Why is the below required? What is the difference between WireInit() and Wire() + assign value?

This doesn't work with BoringUtils.bore():

-  val foo = VecInit(xxx.map(_.yyy)).count(a => a)
+ val foo = WireInit(VecInit(xxx.map(_.yyy)).count(a => a))

This does:

-  val foo = VecInit(xxx.map(_.yyy)).count(a => a)
+ val tmp = VecInit(xxx.map(_.yyy)).count(a => a)
+ val foo = Wire(chiselTypeOf(tmp))
+ foo := tmp

Øyvind Harboe

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Mar 14, 2023, 8:26:47 AM3/14/23
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Here is another problem with the LLVM CIRCT generated code, Verilator tells me the generated code has inferred latches and I have warnings as errors enabled in Verilator linting and hence the build fails:

Schuyler Eldridge

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Mar 14, 2023, 10:57:24 AM3/14/23
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I would turn off automatic logic emission with the disallowLocalVariables lowering option to get around this. Automatic logic is the only way that I am aware of to get a locally scoped temporary in Verilog. However, tool support is extremely spotty.

On Mar 14, 2023, at 08:26, Øyvind Harboe <oyvind...@gmail.com> wrote:

Here is another problem with the LLVM CIRCT generated code, Verilator tells me the generated code has inferred latches and I have warnings as errors enabled in Verilator linting and hence the build fails:
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Øyvind Harboe

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Mar 14, 2023, 11:00:10 AM3/14/23
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It is supported, but it would seem that Verilator authors are of the opinion that this syntax infers latches.

Thanks!

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Øyvind Harboe
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Øyvind Harboe

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Mar 15, 2023, 3:42:36 AM3/15/23
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Ah, another snag...

A series of unfortunate events: LLVM CIRCT generates .sv code that causes Verilator to generate a .cpp file where g++ crashes.

g++: internal compiler error: Segmentation fault signal terminated program cc1plus

$ g++ --version
g++ (Ubuntu 12.2.0-3ubuntu1) 12.2.0
Copyright (C) 2022 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Jack Koenig

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Mar 15, 2023, 12:14:24 PM3/15/23
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Which version of CIRCT are you using? 3.6.0-RC2 was released with 1.31.0, there are minor issues in 1.32.0 and 1.33.0, but please also try 1.34.0 and 1.35.0.

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Jack Koenig

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Mar 15, 2023, 12:16:15 PM3/15/23
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It's also worth trying other versions of Verilator. Certainly a segfault in g++ is a bug in g++, but hopefully a different version of Verilator can avoid it. It might also be worth following up with the Verilator devs if it's possible to create a test case.

Øyvind Harboe

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Mar 15, 2023, 12:23:40 PM3/15/23
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1.35.0



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Øyvind Harboe

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Mar 15, 2023, 4:30:18 PM3/15/23
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Yes: a g++ segfault is a g++ bug.

However, verilator can generate C++ code that is atypical and pushes any compiler off the cliff. clang doesn't even finish in hours on this file, so who knows if it will crash in the end? 

I suspect the problem is that verilator is generating C++ code that, in my case, has ca. 40000 local C++ objects. I've in a previous life seen that g++ will run pathologically slow if you have tens of thousands of local C++ objects. It is something about exception handling or C++ destructors that make g++ take forever to run on these sort of .cpp files.

So the question becomes: what sort of Chisel code generates Verilog code where verilator has thousands of local C++ objects so that g++ crashes :-)

This is a Lemony Snicket bug: a series of unfortunate events...
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