Generating verilog code using my plugin to scala compiler

[Vikas Chauhan]

Hello Sir,

   I am using following command to compile sample codes available on web page. scalac -cp chisel-2.1-SNAPSHOT.jar  SimpleAlu.scala  -Xplugin:MyPlugin.jar and to generate corresponding verilog code i am using this command  scala -cp "chisel-2.1-SNAPSHOT.jar:." Example --v

Now i want to generate verilog for sodar cores( all cores) with my plugin, as each stage is having lots of dependencies and having separate main files(top.scala). I am finding it tough to resolve those dependencies, can you please help me out in finding a way to generate verilog for sodar cores by using my plugin to scala compiler.

Regards,
Vikas chauhan

[Christopher Celio]

You should have a read through the FAQ provided for Sodor on its github page at (https://github.com/ucb-bar/riscv-sodor#about-the-sodor-processor-collection).

While it's a fairly trivial change to generate Verilog from the Sodor build system (as discussed in the FAQ - https://github.com/ucb-bar/riscv-sodor#faq), Sodor does not provide any Verilog testharness or FPGA wrappers, so there's not much use in generating Verilog.

If you want to generate code with your plugin, you'll want to use the existing Sodor build system, and I believe you want to modify "prefix.mk", and modify the SBT variable which invokes Scala/Chisel.


-Chris