Specifying Verilog module names

[Øyvind Harboe]

Is there a way to specify the Verilog module names?

Good names make it easier to navigate the Verilog in downstream tools.

Cheers,

[waleed....@iiu.edu.pk]

You can do it through annotation by mapping the module name-in-chisel to your desired module name-in-verilog
Try something like

import chisel3.experimental.{annotate, ChiselAnnotation}

annotate(new ChiselAnnotation { def toFirrtl = CustomRename(Map("Queue", "QueueWithBetterName")) })

Maybe this would help

[Øyvind Harboe]

This looks promising, but I wasn't able to guess all the import needed for CustomRename

Where would I start reading docs on this?

[Jack Koenig]

I'm not sure what exactly Waleed is referring to, but for modules that you write, you can override desiredName to influence the Verilog module naming: https://www.chisel-lang.org/chisel3/docs/explanations/naming#set-a-module-name

It's generally a good idea to use parameters in naming common modules (to avoid collisions and thus numerical suffix instability).

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[Øyvind Harboe]

Thanks!

I want to name the Verilog based upon parameter names to the module.

However, the documentation says "If you want to specify the module’s name (not the instance name of a module)"

It's unclear to me what the difference between module name and instance name is.

What are the requirements for instance names?

Is it enough that that a combination of parameters generates a unique name and always the same name for the same parameters?

Non-sequitor: google can see these pages, but apparently there's not a lot of links to them...  I should have read these docs before obviously.

[Jack Koenig]

The previous section in that doc talks about how to set the instance name (although does not include an example): https://www.chisel-lang.org/chisel3/docs/explanations/naming#suggest-a-signals-name-or-the-instance-name-of-a-module

The instance name is the name of the Module within its parent

class MyModule extends Module {

  ...

  val myQueue = Module(new Queue(...))

}

myQueue is the instance name of a module who's module name is Queue (probably with some _# suffix due to collisions).

The docs could be a little more clear on these distinctions, if you have any thoughts/suggestions, feel free to PR some changes https://github.com/chipsalliance/chisel3/blob/master/docs/src/explanations/naming.md and we can discuss on the PR

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[Øyvind Harboe]

Aha!

I think about "instance name" as an identifier name.

Scala uses identifier too, it seems like "identifier" is the term of art for any language I quickly checked.  Looks like Verilog too uses identifier.

https://www.scala-lang.org/files/archive/spec/2.12/02-identifiers-names-and-scopes.html

https://www.hdlworks.com/hdl_corner/verilog_ref/items/Identifier.htm

To me it would be clearer if the documentation talked about setting the name of the identifier of wires, registers and modules in Verilog.

It would also be helpful with a reference to Verilog language documentation site where users can bottom out on Verilog terminology, etc.

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Øyvind Harboe
+4791786146