FSM issue

[Hauk Li]

Hi all,

I Write some code to test a Finite State Machine, the code is:

package sqibus

import Chisel._

class sqibridge extends Component {

val io = new Bundle {

/** SQI Interface

*/

val csn = Bits(INPUT, 1)

val sck = Bits(INPUT, 1)

val dio = Vec(4) { UFix(width = 4) }

/** Local Bus

*/

val addr = Bits(OUTPUT, 16)

val read = Bits(OUTPUT, 1)

val rdata = Bits(INPUT, 8)

val write = Bits(OUTPUT, 1)

val wdata = Bits(OUTPUT, 8)

}

/** edge detect

*/

def isRising(x : Bool) = x && !Reg(x)

def isSetting(x : Bool) = !x && Reg(x)

val shiftCounter = Reg(resetVal = UFix(0), width = 12)

val instReg = Reg(resetVal = UFix(0), width = 8)

val addrReg = Reg(resetVal = UFix(0), width = 16)

val lenReg = Reg(resetVal = UFix(0), width = 8)

/** FSM

*/

val s_idle :: s_ins :: s_addr :: s_len :: s_data = Enum(5){ UFix() }

val state = Reg(resetVal = s_idle)

switch (state) {

is (s_idle) {

shiftCounter := UFix(0)

when (isSetting(io.csn)) { state := s_ins }

}

is (s_ins) {

when (isRising(io.sck)) { instReg := instReg << UFix(1) | io.dio(0) }

when (shiftCounter === UFix(7)) {

shiftCounter := UFix(0)

state := s_addr

}

}

is (s_addr){

when (isRising(io.sck)) {

addrReg := addrReg << UFix(4) | io.dio(0) << UFix(3) |

io.dio(1) << UFix(2) | io.dio(2) << UFix(1) | io.dio(3)

}

when (shiftCounter === UFix(3)) {

shiftCounter := UFix(0)

state := s_len

}

}

is (s_len) {

when (isRising(io.sck)) {

lenReg := lenReg << UFix(4) | io.dio(0) << UFix(3) |

io.dio(1) << UFix(2) | io.dio(2) << UFix(1) | io.dio(3)

}

when (shiftCounter === UFix(1)) {

shiftCounter := UFix(0)

state := s_data

}

}

}

}

but eclipse gives a error message : overloaded method value := with alternatives: [T <: Chisel.Data](src: T)Unit <and> (src: 

 Chisel.UFix)Unit <and> (src: Chisel.Fix)Unit <and> (src: Chisel.Bool)Unit cannot be applied to  (List[Chisel.UFix])

and no syntax error occured when i comment "state := s_data"

sorry for my poor english，but it seems no problem in the code

any help ?

regards

Hauk

[Hauk Li]

oh, i found it, i missed adding "Nil" at "val s_idle :: s_ins :: s_addr :: s_len :: s_data  = Enum(5){ UFix() }"

fix : 

        val s_idle :: s_ins :: s_addr :: s_len :: s_data :: Nil = Enum(5){ UFix() }

[Sebastien Mirolo]

Great! I could figure out why it would not work off the top of my head :).

Thanks,

Seb.

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