$Display of chisel

[gopinathan]

Hello

I want to use the $Display of verilog in chisel, what shall i use it here

Regards

Gopinath

[Jonathan Bachrach]

use printf, sprintf and assert with format strings and signals arguments.  

  printf(“PC = %d\n”, pc)

they can be conditionally executed as well.  

  when (halt) {

     printf(“HALT %d\n”, pc)

     …

  }

they work with both the c++ and verilog backends.  they’re very useful for debugging.

it used to be documented but somehow it got removed by accident.  we’re working on getting their doc back in.

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[Dan Luu]

I suppose this is something that will be covered when the
documentation is restored, but how should I print extra debug
information in a test?

I tried adding a printf to a module and running the test for it, and I
don't see anything displayed (although I do see the printf in the
generated .cpp). Just so we're on the same page, if I add

printf("-------------------IO.SEL PRINT STATEMENT %d\n", io.sel)
to Mux2.scala in the chisel-tutorial
and then I run
run Mux2 --backend c --targetDir ../emulator --compile --test --genHarness

I don't get the output of that printf anywhere. Presumably, I could
sprintf the info and then output that to a file, but I'm guessing
that's not the best way to get a debug print statement.

A related and more general question is, what's the recommended method
for testing and debugging modules?


Thanks,
Dan

> https://groups.google.com/d/msgid/chisel-users/40E65C0D-BCFA-4B22-8980-F2849F98F55F%40gmail.com.

[gopinathan]

I used a small code just to display it in the verilog file, but it is not, Here is the code

import Chisel._

import Node._

import scala.collection.mutable.HashMap

import Literal._

import scala.util.Random

class And1 extends Module {

  val io = new Bundle {

    val Instruction        = Bits(INPUT, 32)

    val result   = Bits(OUTPUT, 32)

}

println ("Gopi")

}

class And1Tests(c: And1) extends Tester(c, Array(c.io)) {

  defTests {

    var allGood = true

    val vars    = new HashMap[Node, Node]()

      for (i2 <- 0 until 16){

      vars(c.io.Instruction) = Bits(i2)

          allGood = step(vars) && allGood

}

    allGood

  }

}

object And1 {

    def main(args: Array[String]): Unit = {

        //chiselMainTest(Array[String]("--compile","--test","--backend", "c", "--genHarness"),

chiselMainTest(Array[String]("--compile","--backend", "v"),

           () => Module(new And1())){c => new And1Tests(c)}

}

}

The generated verilog file is

module And1(

    input [31:0] io_Instruction,

    output[31:0] io_result

);

endmodule

I couldn find the display at all.... 

Regards

Gopinath

[Jonathan Bachrach]

Printf not println

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[gopinathan]

Am sorry i tried printf, it did not gave me the $Display of verilog, It gave like,

module And1(input reset,

    input [31:0] io_Instruction,

    output[31:0] io_result

);

  wire T0;

  wire[31:0] T1;

  assign T0 = ! reset;

endmodule

If i increase the number of alphabets in printf ("gopi") it is taing each alphabet as 8 bit width ant it is adding bits to the generated wire  wire[31:0] T1;

Regards

Gopinath

[Christopher Celio]

"I tried adding a printf to a module and running the test for it, and I
don't see anything displayed (although I do see the printf in the
generated .cpp)."

There was a bug in using the Scala-generated test harnesses (as in the chisel-tutorial stuff) in which the Chisel printf talks to stdout, but the test harness talks to the design-under-test via stdout too, so the test harness was sucking up the Chisel printfs and not passing them through to the user's terminal (iirc).  That bug should have been fixed about two weeks ago, so that you should be able to add printf to the chisel-tutorial designs and see the output. 

Now if you write your own test harness, then it's your job to add "dut.print(stderr, stderr)" to it (i forget what the first input is for, but the second input is where your Chisel printf will get sent to). 

"A related and more general question is, what's the recommended method
for testing and debugging modules?"

There are a bunch of ways to approach this. For performance and to run bigger programs, it's best if you can verify the correctness of the design by monitoring the output signals (i.e., the chip can self-check and tell you yah or nah).   No chisel printfs, no vcd files, no debug information.  I do add asserts() to check for error conditions.

If things are going wrong, I rely on Chisel printfs to dump the most relevant state.  Naturally, printing will hurt run time severely (as it would with any C++ program).

If that doesn't help, I then use Chisel printfs in conjuction with vcd output to peer further into the design.  This will require adding the "--vcd" flag to Chisel, which hurts compile (and run) time even more.  You will probably also want to add --ioDebug (to force I/Os to stay named so you can see then in the vcd file).  If you must, add --Debug if you want *all* signals to stay named (which will also really punish compile-time performance).  Only add in as much debug visibility as your patience allows.


I tend to use the Verilog backend when I want vcd output (it tends to keep the hierarchy around without requiring "--debug/--iodebug"), and the C++ backend if I only want the Chisel printf output (it runs faster).  Also depends on how fast your tests fail.  Verilog is fast to compile, slow to run.

The Chisel printf is nice in that both backends can print it out, and if the signal-mangled names change in the backend, you don't have to rewrite your C++ printf code.  It does come with some penalty over a native C++ or Verilog printf.  For starters, you have less control over the ordering of separate Chisel printfs, so I use sprintf to build up a single string to print to the screen. 

Happy debugging,
Chris

[Dan Luu]

Though I'm not clear on the terminology, I don't think I'm modifying
the test harness.

To make sure I'm not using something that's out of date, I tried this
example from the Chisel "Getting Started" doc at
https://chisel.eecs.berkeley.edu/latest/getting-started.html,
completely unchanged from what's on the website, using a build.sbt
that points to latest.release.

package Hello

import Chisel._

class HelloModule extends Module {

val io = new Bundle {}

printf("Hello World!\n")
}

class HelloModuleTests(c: HelloModule) extends Tester(c, Array(c.io)) {
defTests {
true
}
}

object hello {

def main(args: Array[String]): Unit = {

chiselMainTest(Array("--backend", "c", "--genHarness"),
() => Module(new HelloModule()) {
c => new HelloModuleTests(c)
})
}
}

That's supposed to print "Hello, World!\n", but I only get the
following output when I run it:

// COMPILING class HelloModule(0)
started inference
finished inference (2)
start width checking
finished width checking
started flattenning
finished flattening (4)
resolving nodes to the components
finished resolving
started transforms
finished transforms
checking for combinational loops
NO COMBINATIONAL LOOP FOUND

> https://groups.google.com/d/msgid/chisel-users/07346307-3c42-47fa-8079-d62829413de7%40googlegroups.com.

[gopinathan]

Thank you jonathan

I used printf and i get $fwrite in verilog. But what do I need to display i.e $Display. Also If i get a $fwrite in the generated file how will i generate a $fopen or $fclose file. The generated $write generated is like 

if (T860)

        $fwrite(32'h80000002, "OR %b\n", T862);

`endif`ifndef SYNTHESIS

`ifdef PRINTF_COND

    if (`PRINTF_COND)

`endif

 Please elaborate

Regards

Gopinathan