v3.6.0-M2 and BoringUtils and LLVM CIRCT

[Øyvind Harboe]

Is BoringUtils supported yet?

Do I need to do anything to use LLVM CIRCT to generate verilog, or is it default?

[Schuyler Eldridge]

PR is almost merged to CIRCT. It will be on by default.

PR link: https://github.com/llvm/circt/pull/4496

> On Jan 19, 2023, at 06:24, Øyvind Harboe <oyvind...@gmail.com> wrote:
>
> Is BoringUtils supported yet?
>
> Do I need to do anything to use LLVM CIRCT to generate verilog, or is it default?
>

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[Øyvind Harboe]

Nice!

Will I still have to download LLVM CIRCT binaries and put them in the path?

I don't expect Chisel to be compatible with all future version of the rapidly developing LLVM CIRCT, so the version of LLVM CIRCT has to be locked by the Chisel version, no?

Does sbt (Maven?) support distributing binaries such as LLVM CIRCT?

[Schuyler Eldridge]

Initially, yes, you will need to download a binary version of CIRCT and have it in your path. We need to add checking that the CIRCT version is compatible and tell you to update if it's not.

Java publishing does let you package up native binaries. We haven't investigate this. This is intended to be the eventual solution, though.

There are complications here as we don't want to Chisel itself to a version of CIRCT (which moves much faster). Hence, we are expected to introduce a Chisel--CIRCT compiler bridge package that is the thing that includes the native CIRCT binary.

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[Øyvind Harboe]

ETA, purely for planning purposes for this?

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[Schuyler Eldridge]

Boring Util support should be in CIRCT this week or next. Chisel will then support it.

The packaging and publishing is not scheduled right now.

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[Øyvind Harboe]

Thanks!

When is the next prerelease (M3?) scheduled?

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[Jack Koenig]

There is no M3 scheduled, rather, I expect the next release will be Chisel 3.6.0-RC1. My intent would be by the end of next week, hopefully earlier.

Note that this Chisel release is decoupled from the firtool release so once the version of firtool that supports BoringUitls is released (probably 1.29.0), then Chisel 3.6.0-M2 + that version of firtool will support BoringUtils.

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[Øyvind Harboe]

So, near as I can tell support for BoringUtils is now in: https://github.com/llvm/circt/releases/tag/firtool-1.30.0

[Øyvind Harboe]

Some errors with CIRCT 1.30.0:

[error] <stdin>:2:1: error: Unable to apply annotation: {class = "chisel3.util.experimental.ForceNameAnnotation", name = "foo", target = "~bar"}

I'm still getting some of these errors:

[error] <stdin>:2:1: error: Unable to apply annotation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}

val foo = WireInit(chiselTypeOf(bui.io.bar), DontCare)

BoringUtils.bore(xxx, Seq(yyy))

[Schuyler Eldridge]

> On Feb 13, 2023, at 09:17, Øyvind Harboe <oyvind...@gmail.com> wrote:
>
> Some errors with CIRCT 1.30.0:
>
> [error] <stdin>:2:1: error: Unable to apply annotation: {class = "chisel3.util.experimental.ForceNameAnnotation", name = "foo", target = "~bar"}
>
> I'm still getting some of these errors:
>
> [error] <stdin>:2:1: error: Unable to apply annotation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}
> val foo = WireInit(chiselTypeOf(bui.io.bar), DontCare)
> BoringUtils.bore(xxx, Seq(yyy))

Yes, support is on for BoringUtils in CIRCT 1.30.0 and is now being tested as part of Chisel CI since: https://github.com/chipsalliance/chisel3/commit/f1ac9c8019f3e83c663d35426cea47a8194dd894

The forceName API is not supported on components (ports, wires, etc.). This is only supported on the narrow use case of instances. E.g., this is an escape hatch to prevent an instance name from being prefixed during inlining. Is the first error coming from a usage of the forceName API on components? Can you provide more details on what you're doing here?

For the second, that seems weird, though there are a number of situations that are rejected for wiring (invalid annotation target, etc.). Are there any more errors being printed that are not shown in the message?

[Øyvind Harboe]

There are more of the same two error messages, not a third type.

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[Schuyler Eldridge]

That's odd. I would expect to see one of the following other errors:

1. "Cannot resolve a unique instance path from the external module target"
2. "Annotation has invalid target"
3. "Annotation targets non-wipeable operation"
4. "Annotation does not have an associated pin name"
5. "More than one <class> defined for pin"

Do you see any of this? It should directly precede the "Unable to apply" error.

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[Øyvind Harboe]

Yes: you're quite right. I was a bit fast and loose there, answering from my phone.

Here is the complete list of errors I get. I have disabled forceName in Chisel for now:

[error] <stdin>:2:1: error: Annotation targets non-wireable operation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}

[error] circuit AptosNode :

[error] ^

[error] <stdin>:2:1: error: Unable to apply annotation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}

[error] circuit AptosNode :

[error] ^

[error] <stdin>:2:1: error: Annotation targets non-wireable operation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}

[error] circuit AptosNode :

[error] ^

[error] <stdin>:2:1: error: Unable to apply annotation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}

[error] circuit AptosNode :

[error] ^

[error] <stdin>:2:1: error: Annotation targets non-wireable operation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}

[error] circuit AptosNode :

[error] ^

[error] <stdin>:2:1: error: Unable to apply annotation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}

[error] circuit AptosNode :

[error] ^

[error] <stdin>:2:1: error: Annotation targets non-wireable operation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}

[error] circuit AptosNode :

[error] ^

[error] <stdin>:2:1: error: Unable to apply annotation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo", target = "bar"}

[error] circuit AptosNode :

[error] ^

[error] <stdin>:2:1: error: Unable to resolve source for pin: "foo"

[error] circuit AptosNode :

[error] ^

[error] Foo.scala:561:30: error: Wiring Problem source type '!firrtl.uint' does not match sink type '!firrtl.uint<64>'

[error] val xxx = WireInit(io.xxx.yyy)

[error] ^

[error] src/main/scala/ascenium/avalon/AptosSimulationTop.scala:113:30: note: The sink is here.

[error] val xxx = WireInit(UInt(64.W), DontCare)

[Øyvind Harboe]

So I think the problem has to do with width inference, but not exclusively.

Defining wires with uninferred width doesn't seem fix all the problems.

Not sure what's going exactly.