Referencing the implicit clock and reset?

[Jens Korinth]

Hi *!

Existing Verilog modules often do not use .clk and .reset as port names - is there any way to explicitly reference the clock and reset signals automatically generated for Chisel modules? I've got a BlackBox for an existing Verilog module with a Bundle similar to

val io = new Bundle {

  val s_clk = Bool(INPUT)

  val s_rstn = Bool(INPUT)

}

And what I'd like to do is:

io.s_clk := clk

io.s_rstn := ~reset

Is this possible (without modifying the generated Verilog code manually)? Could I, e.g., somehow use an explicit clock to achieve this?

Thanks in advance!

Jens

[Christopher Celio]

In Chisel, reset is already in scope for you to use at will.

io.s_rstn := ~reset

I'm not sure about clock, I don't have any experience with multiple-clock domain stuff which may give you access to clock too. 

-Chris

[Kamyar Mohajerani]

Wouldn't addClock(Driver.implicitClock)and addResetPin(Driver.implicitReset) do the job? I guess you could use any other user-defined clock/reset as arguments.

Kamyar

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[Jens Korinth]

@Chris: Thanks, you're right, I can reference the reset directly!

@Kamyar: Not really; but this is a nice trick to get the clk signal, even if you do not have any registers in the module, I'll keep it in mind. But it does not allow me to re-route the clock to a different port.