Verilog module parameter support?

[Jens Korinth]

I've seen a mention of "first class parameter support" in this post - any progress in that direction? I'm asking because I'd really like to use Verilog module parameters in Chisel generated modules, e.g.

class MyBusModule extends Module {

  val R_DATA_WIDTH = ModuleParam[Int](default = 32)

  ...

  val io = new Bundle {

    ...

    val r_data = UInt(OUTPUT, R_DATA_WIDTH)

    ...

  }

}

which in my vivid imagination would produce something like

module MyBusModule #(

  parameter integer R_DATA_WIDTH = 32;

)

(

  ...

  io_r_data

);

input [R_DATA_WIDTH - 1 : 0] io_r_data;

... 

endmodule

Will Chisel support something similar in the foreseeable future?

[Jonathan Bachrach]

we have never imagined that we would generate verilog parameters.

it's hard to support this in general.

what were you going to use these verilog parameters for?

we were instead going to have first class params in chisel that expand into full elaborated verilog code.

it's impossible to have chisel generators compile into verilog generators without dumbing down chisel.

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[Jens Korinth]

Ah, ok! Basically I'd just like to keep some stuff in the resulting Verilog module configurable, specifically bit widths of I/O ports. This would make it easier to create reusable modules with Chisel for a Verilog/VHDL-based workflow, since one wouldn't have to regenerate the Chisel modules when such details change. 

But basically I'm only having this problem because my top-level is not currently Chisel-generated. Once I migrate the entire design to Chisel, having support for Verilog parameters in the instantiation (which already works) will suffice anyway. :-)

[Jonathan Bachrach]

On Tue, Jul 29, 2014 at 5:24 AM, Jens Korinth <j...@esa.cs.tu-darmstadt.de> wrote:

Ah, ok! Basically I'd just like to keep some stuff in the resulting Verilog module configurable, specifically bit widths of I/O ports. This would make it easier to create reusable modules with Chisel for a Verilog/VHDL-based workflow, since one wouldn't have to regenerate the Chisel modules when such details change. 

But basically I'm only having this problem because my top-level is not currently Chisel-generated. Once I migrate the entire design to Chisel, having support for Verilog parameters in the instantiation (which already works) will suffice anyway. :-)

it's hard to support writing out verilog parameters as chisel parameters are much more powerful.  in short, it's not a priority for us and hard to support in general.

 

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