Generate verilog from chisel

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Shibo Dang

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Oct 20, 2022, 5:26:57 PM10/20/22
to chisel-users
Hi all: 
I am a newbie to Chisel. I try to use the FIFO example in the book to study how to generate the Verilog. I know I need to pass the parameter to:

class RegFifo [T <: Data] (gen:T, depth:Int) extends Fifo(gen:T, depth:Int){
                          ...
}

by 

object  RegFifoDriver  extends  App {
    emitVerilog (new RegFifo (xxx, 8))
}

I just wonder what I should write in 'xxx' area to pass the parameter to T.

Thanks.

Martin Schoeberl

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Nov 1, 2022, 2:00:35 PM11/1/22
to chisel...@googlegroups.com
Hi Shibo,

sorry for the late answer. The FIFO is a generic one and needs a Chisel type to be passed (where you write xxx). For example UInt(16.W), for a FIFO of 16-bit data. Using a component with a generic is not the easiest starting point in learning Chisel ;-)

Cheers,
Martin

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