Deadline extension for: Digital Design and Verification with Chisel (DDVC)

Skip to first unread message

Martin Schoeberl

Apr 11, 2023, 9:44:35 AMApr 11
Call for papers: Digital Design and Verification with Chisel (DDVC)

Performance increase with general-purpose processors has come to a halt. We can no longer depend on Moore's Law to increase computing performance. Building domain-specific hardware accelerators are the only way to achieve higher performance or lower energy consumption. Up to date, hardware design has been a hard, as we are using tools and languages from the last century.

We can learn from software development trends such as agile software development to efficiently develop and verify those accelerators. Chisel as domain specific hardware construction language embedded in Scala leverages actual software methods for hardware construction and verification. 

Topics of interest include, but are not limited to:

* Digital designs using Chisel
* Hardware generators in Scala an Chisel
* Extensions of the Chisel language
* Chisel in teaching
* Chisel libraries
* Design verification with Chisel and ChiselTest
* Formal verification of Chisel designs
* FIRRTL compiler, including CIRCT
* FIRRTL transformation and optimization pathes
* Combining Chisel and UVM or cocotb for verification
* Other hardware construction languages

This special session is part of the Euromicro Conference on Digital System Design (DSD 2023).

2023 DSD and SEAA Conferences is September 6-8, Durres, Albania, Grand Blue Fafa Resort


Paper Submission Deadline: April 30th, 2023
Notification of Acceptance: June 5th, 2023
Camera-Ready Papers: June 19th, 2023

Martin Schoeberl
Special Session Chair

You received this message because you are subscribed to the Google Groups "chisel-users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to
To view this discussion on the web visit
Reply all
Reply to author
0 new messages