FPGA initial value

[Martin Schoeberl]

Hi all,

with designs targeting an FPGA you can do some (dirty?) tricks with initial register values. I use this only at one point in my designs to generate an internal reset signal. (Don’t like to press buttons to start my design) I assume, and give the synthesizer a hint, that usually a register is initialized to 0 after FPGA configuration. From that staring point I count up to generate an internal reset signal. Here some VHDL code for this:

process(clk_int)
begin
if rising_edge(clk_int) then
if (res_cnt /= "111") then
res_cnt <= res_cnt + 1;
end if;
res_reg1 <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2);
res_reg2 <= res_reg1;
int_res <= res_reg2;
end if;
end process;

To hint that res_cnt is initialized with zero at configuration I use following in VHDL:

signal res_cnt : unsigned(2 downto 0) := "000"; -- for the simulation
attribute altera_attribute : string;
attribute altera_attribute of res_cnt : signal is "POWER_UP_LEVEL=LOW”;

I assume these days the first initialization, which originally is only valid for simulation, would be enough to do the trick.

Assume the equivalent Verilog code (for a similar signal) would be:

reg [3:0] cnt = 4'h0;

When using the counter reset trick at Chisel level, the result is a little bit fragile. For smaller counters it did not work (in one FPGA), for larger counters it did.

Question: is there a way to pass this kind of initial value form Chisel towards the Verilog generation?

Cheers,
Martin