FIRRTL and Chisel3 road map

[Jonathan Bachrach]

This is a good opportunity to discuss our Chisel3/FIRRTL plans.  FIRRTL stands for Flexible IR for RTL and is meant to be like an LLVM for hardware.  A compiler for it contains the bulk of the Chisel compiler but has a well defined file format and is implemented as a series of small passes.  It opens up the possibility for other frontends like HLS, "Chixel"s in other PLs, and user contributed compilation passes.  Chisel3 is a much more modular and industrial strength Chisel implementation based around a FIRRTL compiler and a very thin Scala frontend.   It has a few Chisel2 incompatibilities but we have provided a chisel2 -> chisel3 migration facility within chisel2.  

We have currently ported the majority of our RISC-V rocket-chip generator to Chisel3 and are pushing hard to get an alpha version out within a few weeks.  We're also finalizing our FIRRTL spec and should be able to get that out soon for public review and feedback.  From there, we're hoping to get a beta Chisel3 out by the end of this semester.  By then we will have performed a number of tape-ins and have tested it more thoroughly.

Chisel3 has a number of features we hope you will appreciate.  It will include much better documentation and better testing support.  It will rely on Verilator (to start with anyways) for simulation.  It will have improved black boxes, better memory technology mapping and control, DSP support, and multiple clock domain support.  It will be much more modular and open and language neutral and support a repository of hardware components.  

Getting Chisel3/FIRRTL out has been an enormous effort and many people have been involved.  We have an enormous amount of Chisel code written that we have to migrate forward and keep working and a number of folks have been involved during this transition.  We've been working on Chisel for over five years now, but yet are more excited about Chisel than ever.  We've learned a bunch and are in a great position to improve upon our strong foundation.  Thanks for your patience and continued interest in Chisel.

[Edmond Cote]

Thank you for the update. Looking forward to hearing more.

-Ed

[Marek Ciepłucha]

Hi All,

First of all, thank you for this great work and promising results.

I have several comments.

1. What are the benefits of the FIRRTL over Verilog? Verilog can be used at different levels of abstraction, I believe that a Verilog could be a FIRRTL or, at least LoFIRRTL. After reading the spec I can see no real benefits for EDA tools. What you describe as a FIRRTL lowering transformations, is indeed an elaboration done by synthesis tools with some syntax tricks. For me it looks rather that FIRRTL is actualy a "lower front-end" instead of an intermediate representation. However, this opinion is based on my hardware background (instead of software). My understanding of real intermediate layer for hardware is rather combination of functional (HDL), timing (SDC) and power (UPF) requirements in a consistent form. 

2. Why you decided to use Verilator? As I understand (correct me if I am wrong), the advantage of the Chisel HLS features is that actually you benefit from the functional programming syntax and therefore, producing a good quality Scala code gives you a simulation boost. Verilator-based approach seems to have a form: Scala -> FIRRTL -> HDL (Verilog) -> C++. Most simulators today work according to the scheme of translating HDL into C code. 

The power I can see in Chisel is that you can write a readable and consistent HDL code more effectively than in Verilog. Moreover, this is a high-level code that can be compiled and verified without the simulator. I will be grateful, if you could explain a bit more what you intend to achieve using the approach presented in Chisel3.  

Thanks and regards.

Marek Ciepłucha

[Jonathan Bachrach]

On Tue, Mar 8, 2016 at 1:49 AM, Marek Ciepłucha <mcie...@gmail.com> wrote:

Hi All,

First of all, thank you for this great work and promising results.

I have several comments.

1. What are the benefits of the FIRRTL over Verilog? Verilog can be used at different levels of abstraction, I believe that a Verilog could be a FIRRTL or, at least LoFIRRTL. After reading the spec I can see no real benefits for EDA tools. What you describe as a FIRRTL lowering transformations, is indeed an elaboration done by synthesis tools with some syntax tricks. For me it looks rather that FIRRTL is actualy a "lower front-end" instead of an intermediate representation. However, this opinion is based on my hardware background (instead of software). My understanding of real intermediate layer for hardware is rather combination of functional (HDL), timing (SDC) and power (UPF) requirements in a consistent form. 

FIRRTL represents a very simple IR with very focussed functionality and tight semantics.  This is extremely important for writing transformation passes.  Secondly, HiFIRRTL includes some really nice conveniences like richer types, unspecified (to be inferred) widths, conditional assignments etc that are nice to generate during transformation passes.  Thus although the lowering between Hi and Lo FIRRTL is a bunch of work that we did in chisel2 it is useful for writing snippets of Hi FIRRTL.  Finally, we also are working on some level of abstraction in FIRRTL which allow better technology mapping.   

Currently we are improving Chisel3 to meet our tape out needs and those of alpha users and at that point we will have more confidence with it meeting what we see as the core set of needs.

 

2. Why you decided to use Verilator? As I understand (correct me if I am wrong), the advantage of the Chisel HLS features is that actually you benefit from the functional programming syntax and therefore, producing a good quality Scala code gives you a simulation boost. Verilator-based approach seems to have a form: Scala -> FIRRTL -> HDL (Verilog) -> C++. Most simulators today work according to the scheme of translating HDL into C code. 

We're still evaluating Verilator.  BTW Verilator does translate Verilog to C++.  There are at least three big advantages: (1) reduce more possibilities of mismatch between C++ and Verilog (especially when doing expensive tape-outs), (2) reduce our maintenance effort of C++ backend, and (3) focus energy on Verilog backend which can always use improvement.  In the case that Verilator doesn't deliver then we will probably go with an LLVM backend that is mostly "complete" (in that elusive sense). 

 

The power I can see in Chisel is that you can write a readable and consistent HDL code more effectively than in Verilog. Moreover, this is a high-level code that can be compiled and verified without the simulator. I will be grateful, if you could explain a bit more what you intend to achieve using the approach presented in Chisel3.  

the big win in chisel3 is to have an open compiler where people can contribute new front ends, transformation passes, and backends.  in particular, we've written a bunch of transformation passes in chisel2's ad hoc IR and are excited to rewrite them in FIRRTL and to create a library of these passes.  it's been a ton of work to formalize the internals of chisel but we think it offers enormous benefits.  one big thing to us is to create a much more industrial strength offering where it is better documented and better engineered and more reliable and seamless.  this way we can we have more confidence to get behind it and to invite world wide participation moving forward.

thanks for your interest!

 

Thanks and regards.

Marek Ciepłucha

W dniu wtorek, 9 lutego 2016 19:14:11 UTC+1 użytkownik Edmond Cote napisał:

Thank you for the update. Looking forward to hearing more.

-Ed

On Monday, January 25, 2016 at 5:05:19 PM UTC-8, Jonathan Bachrach wrote:

This is a good opportunity to discuss our Chisel3/FIRRTL plans.  FIRRTL stands for Flexible IR for RTL and is meant to be like an LLVM for hardware.  A compiler for it contains the bulk of the Chisel compiler but has a well defined file format and is implemented as a series of small passes.  It opens up the possibility for other frontends like HLS, "Chixel"s in other PLs, and user contributed compilation passes.  Chisel3 is a much more modular and industrial strength Chisel implementation based around a FIRRTL compiler and a very thin Scala frontend.   It has a few Chisel2 incompatibilities but we have provided a chisel2 -> chisel3 migration facility within chisel2.  

We have currently ported the majority of our RISC-V rocket-chip generator to Chisel3 and are pushing hard to get an alpha version out within a few weeks.  We're also finalizing our FIRRTL spec and should be able to get that out soon for public review and feedback.  From there, we're hoping to get a beta Chisel3 out by the end of this semester.  By then we will have performed a number of tape-ins and have tested it more thoroughly.

Chisel3 has a number of features we hope you will appreciate.  It will include much better documentation and better testing support.  It will rely on Verilator (to start with anyways) for simulation.  It will have improved black boxes, better memory technology mapping and control, DSP support, and multiple clock domain support.  It will be much more modular and open and language neutral and support a repository of hardware components.  

Getting Chisel3/FIRRTL out has been an enormous effort and many people have been involved.  We have an enormous amount of Chisel code written that we have to migrate forward and keep working and a number of folks have been involved during this transition.  We've been working on Chisel for over five years now, but yet are more excited about Chisel than ever.  We've learned a bunch and are in a great position to improve upon our strong foundation.  Thanks for your patience and continued interest in Chisel.

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