Chisel v3.6.0-RC2 example of slow verilator compilation

[Øyvind Harboe]

This code, when generated with LLVM CIRCT, takes a long time to compile:

https://scastie.scala-lang.org/nXXNW6C1R1GLZbq5YcmqHw

I think by scaling this up or tweaking it in some way, a crash in g++ can be reproduced.

verilator -cc test/Example.sv

# this takes at least 30 seconds on my machine, which is surprising

make -f VExample.mk

object GenerateExample extends App {

class Example extends Module {

val a = IO(Input(UInt(16384.W)))

val out = IO(Output(UInt(16384.W)))

out := (0 until 16384 by 4)

.map { i =>

a(i + 3, i)

}

.reduce(_ ## _)

}

new circt.stage.ChiselStage()

.execute(

args,

Seq(

circt.stage.CIRCTTargetAnnotation(circt.stage.CIRCTTarget.Verilog),

ChiselGeneratorAnnotation(() => new Example),

circt.stage.FirtoolOption("--lowering-options=disallowPackedArrays,disallowLocalVariables"),

circt.stage.FirtoolOption("--split-verilog"),

circt.stage.FirtoolOption("--dedup"),

circt.stage.FirtoolOption("--strip-debug-info"),

circt.stage.FirtoolOption("--extract-test-code"),

circt.stage.FirtoolOption("-o=test/")

)

)

}

[Jack Koenig]

Can you see what happens if you give the following options to Verilator?

--output-split 20000
--output-split-cfuncs 20000

Basically every use I see of Chisel + Verilator uses these options to split up the emitted C++

Other values I've seen are 1000000 for output-split and 5000 for output-split-cfuncs.

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[Øyvind Harboe]

I tried that...

I will try upgrading verilator, see link below.

However, I think this first requires fixing another bug in my code, a good thing. It's a windy road... but I think it will all work out in the end for the better... My overall experience with upgrading to LLVM CIRCT and Chisel 3.6.2 so far is that it is about paying back technical debt and improving my code, which is all good, but it is a bit of work and it is probably a good idea to set aside a bulk of time to work on it for bigger projects.

https://github.com/verilator/verilator/issues/4026#issuecomment-1470864741

Fingers x'ed this is the last hurdle :-)

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Øyvind Harboe
+4791786146

[Øyvind Harboe]

Ah, so I was able to get rid of the crash/compile problem by breaking out the code into a separate module so that I don't get a bizillion local C++ objects.

The next hurdle, is that I had some perl code that injected /* verilator public */ to some module input/output signals. This perl script is broken because the perl will also insert /* verilator public */ elsewhere into the code.

I don't know if there is a way to get Chisel + LLVM CIRCT to insert /* verilator public */ comments after specific input/output signals in a module definition.

However, in my case, I can use BoringUtils.bore() instead. This gives allows me to create top-level signals that I can inspect in C++ in the verilated code.

Onwards!

[Øyvind Harboe]

So BoringUtils.bore() instead of /* verilator public */ hacks seems to have done the trick.

I *think* I've gotten to the bottom of it now and that I'm fully converted to LLVM CIRCT, though it will be some time before it's all regression tested...

[Øyvind Harboe]

Yep... passed all the tests on Quartus, FPGA and OpenROAD... :-)

[Jack Koenig]

Awesome to hear :) Thanks Øyvind!

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