Left shift possible code gen error

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ashrir...@gmail.com

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May 1, 2022, 12:47:33 PMMay 1
to chisel-users
Chisel version : 3.4.4

I am getting a strange error when the FIRRTL is translating left shifts.
The FIRRTL seems fine. Seems like the error is introduced in the verilog
This is just a generic ALU. 
Seem to create a strange wire [94:0] _GEN_0 = {{63'd0}, io_in1}; // @[Alu.scala 181:38]
Only happens on left shifts, rights seem fine. Why is it 0 extending io_in1?

Sometimes the zero extension is crazy width such as 52768.


FIRRTL:
  module UALU_3 :
    input clock : Clock
    input reset : Reset
    output io : { flip in1 : UInt<32>, flip in2 : UInt<32>, out : UInt<32>}

    node in1S = asSInt(io.in1) @[Alu.scala 169:21]
    node in2S = asSInt(io.in2) @[Alu.scala 170:21]
    node _T = add(io.in1, io.in2) @[Alu.scala 175:32]
    node _T_1 = tail(_T, 1) @[Alu.scala 175:32]
    node _T_2 = sub(io.in1, io.in2) @[Alu.scala 176:32]
    node _T_3 = tail(_T_2, 1) @[Alu.scala 176:32]
    node _T_4 = and(io.in1, io.in2) @[Alu.scala 177:32]
    node _T_5 = or(io.in1, io.in2) @[Alu.scala 178:31]
    node _T_6 = xor(io.in1, io.in2) @[Alu.scala 179:32]
    node _T_7 = xor(io.in1, io.in2) @[Alu.scala 180:35]
    node _T_8 = not(_T_7) @[Alu.scala 180:26]
    node _T_9 = bits(io.in2, 5, 0) @[Alu.scala 181:47]
    node _T_10 = dshl(io.in1, _T_9) @[Alu.scala 181:38]
    node _T_11 = bits(io.in2, 18, 0) @[Alu.scala 182:48]
    node _T_12 = dshr(io.in1, _T_11) @[Alu.scala 182:39]
    node _T_13 = bits(io.in2, 18, 0) @[Alu.scala 183:62]
    node _T_14 = dshr(io.in1, _T_13) @[Alu.scala 183:53]
    node _T_15 = asSInt(io.in1) @[Alu.scala 184:49]
    node _T_16 = bits(io.in2, 18, 0) @[Alu.scala 184:65]
    node _T_17 = dshr(_T_15, _T_16) @[Alu.scala 184:56]
    node _T_18 = asUInt(_T_17) @[Alu.scala 184:103]
    node _T_19 = lt(io.in1, io.in2) @[Alu.scala 185:38]
    node _T_20 = gt(io.in1, io.in2) @[Alu.scala 186:38]
    node _T_21 = eq(io.in1, io.in2) @[Alu.scala 187:38]
    node _T_22 = leq(io.in1, io.in2) @[Alu.scala 188:39]
    node _T_23 = geq(io.in1, io.in2) @[Alu.scala 189:39]
    node _T_24 = mul(io.in1, io.in2) @[Alu.scala 192:32]
    node _T_25 = div(io.in1, io.in2) @[Alu.scala 193:32]
    node _T_26 = rem(io.in1, io.in2) @[Alu.scala 194:32]
    node _T_27 = gt(io.in1, io.in2) @[Alu.scala 195:36]
    node _T_28 = mux(_T_27, io.in1, io.in2) @[Alu.scala 195:28]
    node _T_29 = lt(io.in1, io.in2) @[Alu.scala 196:36]
    node _T_30 = mux(_T_29, io.in1, io.in2) @[Alu.scala 196:28]
    io.out <= _T_10 @[Alu.scala 233:10]

Verilog:
module UALU_3(
input [31:0] io_in1,
input [31:0] io_in2,
output [31:0] io_out
);
wire [94:0] _GEN_0 = {{63'd0}, io_in1}; // @[Alu.scala 181:38]
wire [94:0] _T_10 = _GEN_0 << io_in2[5:0]; // @[Alu.scala 181:38]
assign io_out = _T_10[31:0]; // @[Alu.scala 233:10]
endmodule

Øyvind Harboe

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May 7, 2022, 1:49:55 PMMay 7
to chisel-users
That looks correct to me. Maybe a little bit surprising, but correct.

Can you elaborate on why this is not correct?

Can you share the Chisel example when the zero extension is 52768 bits?

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