SInt vs. UInt and division

[Øyvind Harboe]

The division operator does not appear to be supported for SInt.

Is this intentional?

I thought Verilog could express signed division.

[lae...@berkeley.edu]

Hi,

Signed division seems to work: https://scastie.scala-lang.org/n9L3WlffRwWMvH2ZZXI8NQ

Mixing signed and unsigned values is not supported. You would have to cast the unsigned expression to a signed one.

Hope this helps.

- Kevin

[Øyvind Harboe]

Ah.

Silly me :-)

I was confused, all I was missing was to write:

val a : UInt

val b : UInt

val c : UInt

c := (a.asSInt / b.asSInt).asUInt

// the below will not compile of course
// c := (a.asSInt / b.asSInt)

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Øyvind Harboe
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