SInt vs. UInt and division

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Øyvind Harboe

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Jul 28, 2022, 4:35:37 AMJul 28
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The division operator does not appear to be supported for SInt.

Is this intentional?

I thought Verilog could express signed division.

lae...@berkeley.edu

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Jul 29, 2022, 7:38:41 PMJul 29
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Hi,


Mixing signed and unsigned values is not supported. You would have to cast the unsigned expression to a signed one.

Hope this helps.

- Kevin

Øyvind Harboe

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Jul 30, 2022, 3:21:33 AMJul 30
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Ah.

Silly me :-)

I was confused, all I was missing was to write:

val a : UInt
val b : UInt
val c : UInt
c := (a.asSInt / b.asSInt).asUInt

// the below will not compile of course
// c := (a.asSInt / b.asSInt)


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