Disable a block in Chisel

[Poly Lee]

Hi I used to write verilog code just like this, to break a loop:

begin : xxx

    for(loop_index = 0; loop_index < VECTOR_LENGTH; loop_index = loop_index + 1)

    begin

        if(vector_in[loop_index])

        begin

            ...

            disable xxx; 

        end

    end

end

Is there some direct way I can do this in Chisel? 

[Edward Wang]

https://alvinalexander.com/scala/scala-break-continue-examples-breakable has some examples on how to break out of Scala loops.

[Poly Lee]

Thanks but it seems I couldn't use in Chisel structure like 

when (something) {

  ...

  break

[Jack Koenig]

Hello,

If you can share a little bit more about what you're trying to do, maybe we can provide an alternative way to achieve the same goal?

The reason why you cannot return in when blocks is that fundamentally, using Chisel is writing software to construct a hardware rather than writing code to be behaviorally synthesized. It is important to think about Chisel as explicitly describing the wires, registers, memories, and logic in your circuit. You can then leverage the power of Scala to parameterize and write program to perform this hardware construction.

We usually differentiate between *elaboration* and the actual generated *hardware*. For example

val w = Wire(UInt(8.W))

if (condition) {

  w := 10.U

} else {

  w := 20.U

}

This snippet uses "if" which is a Scala construct matching if in any other language. Since if is a Scala construct, this condition is evaluated when the program is generating our hardware. That means, that statically, either the "then" or the "else" block executes. In our actual hardware, in simulation or in silicon, wire is either always 10, or always 20. Assuming condition is true, this corresponds to the Verilog:

wire [7:0] w = 10;

Note that 20 is no where to be seen, only the "then" block of the "if" was executed when the Scala program ran.

Alternatively, if we consider Chisel's "when" construct, this is a syntactically convenient way to create mux(es):

val w = Wire(UInt(8.W))

when (condition) {

  w := 10.U

} .otherwise {

  w := 20.U

}

In this case, rather than condition being an elaboration-time (ie. statically known) Boolean, it is a Chisel Bool, a signal or wire actually present in the generated hardware. Thus this corresponds to the Verilog:

wire condition = // something

wire [7:0] w = condition ? 10 : 20;

Now, you may be wondering what any of this has to do with *return*. The important thing to know is that return is a Scala construct, so it is relevant at elaboration time but has no realization in hardware. If you look at the when/.otherwise block above, *both* blocks execute when the Scala program runs. You can think about the when block as recording "condition" as the select signal for a Mux, and then registering 10 and 20 as the true and false inputs for the Mux. Thus, as far as Scala is concerned, both the when block, and the .otherwise block execute. The key insight is the conditional is preserved through to the hardware, whereas on the if, else only one side or the other makes it through.

I hope this explanation helps at least a little bit. But in any case, please let us know what you're trying to do and we'll do our best to guide you in the right direction!

--
You received this message because you are subscribed to the Google Groups "chisel-users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to chisel-users...@googlegroups.com.
To post to this group, send email to chisel...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/chisel-users/961c970c-967a-4c2b-aae4-dcadce702a5f%40googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[Poly Lee]

Sorry for my indistinct description. I am new to Chisel and am trying to translate some verilog codes made by others into chisel code. There are a few modules I met. They use a similar pattern, which is exiting from a loop. One example is a module trying to find out the highest positive index from vector_in and it writes like this:

integer loop_index;
always@*
begin : Find_First_One
    first_one_index_out  <= {(MAX_OUTPUT_WIDTH){1'b0}};
    one_is_found_out     <= 1'b0;

    for(loop_index = 0; loop_index < VECTOR_LENGTH; loop_index = loop_index + 1)
    begin
        if(vector_in[loop_index])
        begin

            first_one_index_out  <= loop_index;
            one_is_found_out     <= 1'b1;
            disable Find_First_One; 
        end
    end
end

as we know this correct verilog code can be able to be synthesized just like you said, "generated into hardware", even if it tries to BREAK the loop!

However I found it difficult to implement similar function in chisel and so far for this special one I have used a ugly but working chisel code goes like this:

for (loop_index <- 0 until VECTOR_LENGTH) {

if (loop_index > 0) {

vector_in_or(loop_index) := vector_in_or(loop_index - 1) | io.vector_in(loop_index)

when(vector_in_or(loop_index).toBool && (!vector_in_or(loop_index - 1))) {

first_one_index_out_reg := loop_index.U

one_is_found_out_reg := true.B

}

} else {

vector_in_or(loop_index) := io.vector_in(loop_index)

when(vector_in_or(loop_index).toBool) {

first_one_index_out_reg := loop_index.U

one_is_found_out_reg := true.B

}

}

}

But it is too lengthy for all the rest verilog patterns. I would really appreciate it if you can provide a general solution. Thanks!

[Jack Koenig]

I apologize for my delay in responding. There are a few ways you could accomplish this, from more similar to the Verilog to very Scala-y.

I would encourage you (and everyone new to Chisel) to check out the Chisel Bootcamp: https://github.com/freechipsproject/chisel-bootcamp

It does a fantastic job of explaining Chisel and Scala as you go, and lets you experiment with code and examples in a Jupyter notebook.

Similar to Verilog:

// Picking the size of the Vector as the value if no 1 is found

val valueIfNotFound = VECTOR_LENGTH.U

val found_index = WireInit(valueIfNotFound)

for (i <- (VECTOR_LENGTH - 1) to 0 by -1) {

  when (vector_in(i)) {

    found_index := i.U

  }

}

This solution takes advantage of Chisel's *last connect semantics*, ie., the last connection wins. You can see much more information about last connect semantics in the bootcamp here:

https://github.com/freechipsproject/chisel-bootcamp/blob/c65757afb9cbbd8987b57440da275eb921a29b2b/2.3_control_flow.ipynb

A more Chisel-y solution uses the built-in PriorityMux. This function accepts two parallel sequences: a sequence of selection bits and a sequence of values. It propagates the value corresponding to the first asserted select bit:

import chisel3.util.PriorityMux

val indices = (0 until VECTOR_LENGTH).map(_.U)

val found_index = PriorityMux(vector_in, indices)

In this solution, we simply pass the vector itself as the select bits, and construct a sequence of indices corresponding to each element of the input vector.

An even more Chisel-y solution would be to take advantage of indexWhere. I'll leave this one as an exercise for the reader but the Chisel Bootcamp helps teach enough Chisel and Scala to come up with this solution :)

--

You received this message because you are subscribed to the Google Groups "chisel-users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to chisel-users...@googlegroups.com.
To post to this group, send email to chisel...@googlegroups.com.

To view this discussion on the web visit https://groups.google.com/d/msgid/chisel-users/f0c79707-d1b4-4edb-84fd-ef2a39d9c4d6%40googlegroups.com.

[Poly Lee]

Thanks. Problem solved!