Hi all,
I'm trying to understand DecoupledIO. Here's a simple design:
class Dummy() extends Module {
val io = IO(new Bundle {
val in = Input(DecoupledIO(UInt(10.W)))
})
}
The Verilog interface generated for this module is (correctly) as below:
module Dummy(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [9:0] io_in_bits
);
However, when I try to assign something to the 'ready' from within the module, it results in a Chisel compiler error:
io.in.ready := Bool(true) // Within the 'Dummy' module, causes the error below:
[error] (run-main-e) chisel3.internal.ChiselException: Connection between sink (chisel3.core.Bool@10) and source (chisel3.core.Bool@15) failed @: Sink is unwriteable by current module.
chisel3.internal.ChiselException: Connection between sink (chisel3.core.Bool@10) and source (chisel3.core.Bool@15) failed @: Sink is unwriteable by current module.
at chisel3.internal.throwException$.apply(Error.scala:13)
at chisel3.core.Data.connect(Data.scala:145)
at chisel3.core.Data.$colon$eq(Data.scala:204)
at example.Dummy.<init>(Dummy.scala:15)
...
1. Why is this assignment wrong? How should one use DecoupledIO?
2. I noticed that EnqIO, DeqIO, and DecoupledIO all generate the same interface. Are they all functionally equivalent?
Thanks,
Raghu