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I try to write to mailing lists with a thought to that Google will be indexing the content. This as a way to pay back for all the useful information I find when googling myself....
It takes a bit of practice to read the below, but my colleague who doesn't know Chisel or FPGAs, but is quite adept at Haskell could read the code below without explanation.To someone well versed in Verilog only, the code below is humiliating. Especially considering that when it comes to quality of synthesis, it's the end of the line...io.result := VecInit(leftRotateValue.map(_.asBools).transpose.map(VecInit(_).asUInt).map(value =>((value | (value << (resultWidth / symbolSize))) << io.leftRotate)(2 * resultWidth / symbolSize - 1,resultWidth / symbolSize)).map(_.asBools).transpose.map(VecInit(_).asUInt)).asUIntThis is really cool. Is there any chance you can elaborate on how you tuned your code into the final state? That would be really great!
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