Can I have SyncReadMem() and firtool output a file with a single clock?

[Øyvind Harboe]

I am getting one clock per read and write port, even if there is a single clock in my design where SyncReadMem() is invoked.

Is there a way to tell SyncReadMem() to generate a .sv file for this SRAM with a single clock?

module registers_32x64(

input [4:0] R0_addr,

input R0_en,

R0_clk,

input [4:0] W0_addr,

input W0_en,

W0_clk,

input [63:0] W0_data,

input [7:0] W0_mask,

input [4:0] W1_addr,

input W1_en,

W1_clk,

[Schuyler Eldridge]

There is currently no way to do this. Keeping this as-is, where you get a memory (or a blackbox module) with this predictable lowering has ABI benefits---you know what you're going to get and it's not a function of whether two clocks are wired together trivially or, as some might expect, in a more complicated way somewhere earlier in the hierarchy.

Chisel or FIRRTL don't have the ideal representation for clocks and resets as these are closer to "global resources" rather than things which are ports and can be put into wires or registers. Reworking Chisel in this direction would help with the desired emission strategy as there is then an unambiguous way to say that two ports of a memory have _the same clock_ as opposed to _the same wire_.

tl;dr: Wiring the ports together is the right way to proceed or to put the memory in a wrapper module in Chisel.

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[Øyvind Harboe]

I'm tinkering with OpenROAD flow scripts and MegaBoom.

There are ca. 100 SRAMs in MegaBoom and each of these SRAMs have various read and write ports, so that's *at least* different 200 clock names... If they were *all* called "clock", then things would be a LOT simpler w.r.t. setting up the backend scripts, such as the .sdc file...