Unused bits in Verilog

[Øyvind Harboe]

Unused outputs for a module are trimmed, but unused bits are not. At least not always.

Should Chisel by design trim unused bits as well as unused outputs of a module?

[waleed....@iiu.edu.pk]

I don't think Chisel should trim the unused bits from the output. Because it will cause very much distress in verification.

Also if you are worried from the perspective of hardware then synthesizer will do it.

On the unused output, on a personal point I think that too should not be trimmed.
But if Chisel sometimes does that, I have no problem with that ;)

[Kevin Laeufer]

Hi Øyvind,

Trimming unused bits is a bit harder to do then removing unused signals.
Especially if you allow trimming unused bits _inside_ a signal you would
have to split said signal into two (or more). This would leave us
without a clear path to giving the two new signals a decent name in the
generated Verilog.

If you only trim unused bits at the front or back of the signal, that
would be feasible but isn't really a priority since Synthesis tools will
probably do the same optimization and trimming those bits doesn't really
help that much with making the generated Verilog more readable.


Regards,
Kevin

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[Øyvind Harboe]

Makes sense.

Trimming signals at the beginning or end would be adequate for the cases that I've run into. Especially most significant bits.

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Øyvind Harboe
+4791786146

[Øyvind Harboe]

The advantage of trimming the signals would be that the generated Verilog would be closer to hand-optimized code and it would reduce FUD (fear uncertainty doubt).

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Øyvind Harboe
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