v3.6.0-M2 and LLVM CIRCT 1.30.0 problem

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Øyvind Harboe

Feb 14, 2023, 8:42:34 AM2/14/23
to chisel-users
I get these problems when trying to generate Verilog using CIRCT.

I only get one at the time, if I fix one, I get another. It seems like compilation is aborting upon hitting one of these.  Intentional?

[error] Foo:23:42: error: Wiring Problem source type '!firrtl.uint' does not match sink type '!firrtl.uint<64>'
[error]   val foo = WireInit(io.bar)
[error]                                          ^
[error] Bar.scala:123:18: note: The sink is here.
[error]   val xxx = Wire(new FooBar())

The fix is to change:

val foo = WireInit(io.bar)


val foo = Wire(chiselTypeOf(io.bar))
foo := io.bar

Øyvind Harboe

Feb 14, 2023, 9:07:28 AM2/14/23
to chisel-users
I've whittled away all the errors above in my design, and now I'm left with this error. I have removed all use of dontTouch() in my design.

How do I track this one down?

[error] Exception in thread "main" circt.stage.phases.Exceptions$FirtoolNonZeroExitCode: firtool returned a non-zero exit code
[error] ------------------------------------------------------------------------------
[error] ExitCode:
[error] 1
[error] STDOUT:
[error] STDERR:
[error] <stdin>:3:10: warning: unprocessed annotation:'firrtl.transforms.DontTouchAnnotation' still remaining after LowerToHW
[error]   module Foo :
[error]          ^
[error] <unknown>:0: error: destination isn't an inout type
[error] <unknown>:0: note: see current operation: "firrtl.strictconnect"(%102, %108) : (!firrtl.uint<3>, !firrtl.uint<3>) -> ()
[error] <unknown>:0: error: 'firrtl.strictconnect' op LowerToHW couldn't handle this operation
[error] <unknown>:0: note: see current operation: "firrtl.strictconnect"(%102, %108) : (!firrtl.uint<3>, !firrtl.uint<3>) -> ()

Schuyler Eldridge

Feb 15, 2023, 12:35:21 PM2/15/23
to chisel...@googlegroups.com
The issue with BoringUtils should be fixed in 1.31.0 once https://github.com/llvm/circt/pull/4656 lands.

The other issue:

1. You can ignore the warning. That is a bug, but isn't the reason why this is failing.
2. The errors below about `destination isn't an inout type` looks like an actual bug. Is there any way you can provide a reproducible bug report? (The whole design is fine and if you'd rather not share this publicly, you can send it to me directly.)

Øyvind Harboe

Feb 16, 2023, 1:46:09 AM2/16/23
to chisel-users
Another issue I found.

LLVM CIRCT is more forgiving that classic Chisel Verilog generation.

This fails with classic Chisel Verilog generation:

val xxx = Wire(yyy)
BoringUtils.bore(foo, Seq(xxxx))

firrtl.passes.CheckInitialization$RefNotInitializedException:  @[Foo.scala 113:30] : [module blah]  Reference xxx is not fully initialized.

To fix it:

val xxx = Wire(yyy)
xxx := DontCare // Fix!
BoringUtils.bore(foo, Seq(xxxx))

On Tuesday, February 14, 2023 at 2:42:34 PM UTC+1 Øyvind Harboe wrote:

Schuyler Eldridge

Feb 17, 2023, 11:22:44 AM2/17/23
to chisel...@googlegroups.com
This is an intentional feature!

The difference is that with the Scala-based FIRRTL Compiler (SFC), the WiringAnnotations are converted to connections and ports during the middle of the pass pipeline. Initialization checking happens pretty early during the "ExpandWhens" pass. Initialization checking doesn't know about WiringAnnotations so it errors out.

With CIRCT (the MLIR-based FIRRTL Compiler (MFC)), the WiringAnnotations are converted to connections immediately after parsing. When initialization checking happens (also in an "ExpandWhens" pass) everything has already been hooked up.

Øyvind Harboe

Feb 17, 2023, 11:24:38 AM2/17/23
to chisel...@googlegroups.com
👍 Nice! That DontCare requirement always looked  bit odd.

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