Mapping chisel assert(..) statement to assertion in generated Verilog/SVerilog code

[Javed Osmany]

Hello

I am exploring the assert(..) statement in Chisel.

I can add the assert(..) statement in the block.scala or tb_block.scala

During the simulation of block, the assertion fires as required.

However, when i run the sbt command to generate the Verilog code, block.v, the chisel assert(..) is not translated to the corresponding Verilog assertion.

QS: Is it possible to get sbt/firrtl to translate the chisel assert(..) statement into the corresponding Verilog assertion?

Thanks in advance

JO

[Øyvind Harboe]

Yes, that should be possible.

Could you try to write up the example that is causing difficulties here https://scastie.scala-lang.org/9AZWsMbFTpWPfXppd0W8VQ  and post a link for the example so your problem can be investigated?