Synthesize Mem to Block RAM

[Arjun Ramaswami]

Hi everyone,

How can I describe a Mem module in Chisel such that it synthesizes to a Block RAM and not a distributed RAM in an FGPA? 

Looking forward to your replies.

Regards,

Arjun

[Martin Schoeberl]

Hi Atjun,

Block RAMs today need input registers for all ports. Make sure that your read address goes through a register.

See an example here: https://github.com/t-crest/patmos/blob/master/hardware/src/patmos/MemBlock.scala

with the following lines of code relevant to you:

  val mem = Mem(Bits(width = width), size)

  // write

  when(io.wrEna === Bits(1)) {

    mem(io.wrAddr) := io.wrData

  }

  // read

  val rdAddrReg = Reg(next = io.rdAddr)

  io.rdData := mem(rdAddrReg)

Cheers,

Martin

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