I was reading the
Serialization Cookbook recently, and am scratching my head a bit. It seems unnecessarily complicated; I must be missing something.
I have always done parameterization simply through a case class, putting all the module's top-level params in one place, then customizing them at the time of instantiation. The serialization method above seems extremely similar, just more complicated.
For context, I am only using Chisel for standalone module creation, not really focused on trying to use Chisel at the full SoC-level, ChipYard, etc.
What's the shortcoming of a simple case class? What do I get with Serialization that I haven't thought about?
Here's my typical use model.
/** Generate Verilog */
object Main extends App {
val myParams = DynamicFifoParams(
externalRam = true,
dataWidth = 128,
fifoDepth = 32
)
ChiselStage.emitSystemVerilog(
new DynamicFifo(myParams),
firtoolOpts = Array(
"--lowering-options=disallowLocalVariables,disallowPackedArrays",
"--disable-all-randomization",
"--strip-debug-info",
"--verilog",
"--split-verilog",
"-o=generated"
)
)
}