Problem with Chisel 3.6.0 and dontTouch() annotation

[Øyvind Harboe]

I am trying to test out RISC-V BOOM with Chipyard and I'm getting an error message for Chisel 3.6.0.

It seems to have something to do with the dontTouch() annotation.

I seem to vagely recall that this has been fixed in a more recent version of Chisel or firtool?

https://github.com/riscv-boom/riscv-boom/blob/96da674bc97955e7fa068f0a9a1d0a7a479d1d0b/src/main/scala/exu/core.scala#L311

/home/oyvind/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.MegaBoomConfig/chipyard.harness.TestHarness.MegaBoomConfig.sfc.fir:2:1: error: Unable to resolve target of annotation: {class = "firrtl.transforms.DontTouchAnnotation", target = "~TestHarness|BoomCore>debug_brs"}

https://conda.anaconda.org/ucb-bar/linux-64/firtool-1.30.0-0_h1234567_gdb40efbcd.conda

[Øyvind Harboe]

Looks like this Conda channel is quite far behind...

1.54.0 is the most recent version in this link as of writing... https://github.com/llvm/circt/releases

$ conda search firtool --channel ucb-bar
Loading channels: done
# Name                       Version           Build  Channel            
firtool                sifive.1.16.0 0_h1234567_g14ac3cb0e  ucb-bar            
firtool                       1.16.0 0_h1234567_g14ac3cb0e  ucb-bar            
firtool                       1.25.0 0_h1234567_gd0462e7ec  ucb-bar            
firtool              1.29.0.newhammerhotfix 0_h1234567_ga5f6aa51f  ucb-bar            
firtool                       1.29.0 0_h1234567_ga5f6aa51f  ucb-bar            
firtool                       1.30.0 0_h1234567_gdb40efbcd  ucb-bar         
$

[Schuyler Eldridge]

This "could not resolve target of annotation" error is indicating that
in module `BoomCore` there is no port, wire, or register named
`debug_brs`. This is unexpected unless you're mixing and matching
annotation files and FIRRTL files that were not generated by the same
Chisel elaboration. Can you confirm that the module has such a name
inside it?

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[Øyvind Harboe]

On Friday, September 15, 2023 at 6:24:06 PM UTC+2 schuyler...@gmail.com wrote:

This "could not resolve target of annotation" error is indicating that
in module `BoomCore` there is no port, wire, or register named
`debug_brs`. This is unexpected unless you're mixing and matching
annotation files and FIRRTL files that were not generated by the same
Chisel elaboration. Can you confirm that the module has such a name
inside it?

I am mixing and matching configurations indeed. I've only recently started to have a look at Chipyard. I suspect that this problem might go away when I learn more about how to set up a Chipyard configuration properly...

I mangled a sky130hd tutorial for TinyRocket to be able to see if I could generate Verilog files for MegaBoomConfig...

See here. One of the things I tried was to upgrade firtool from 1.30.0, but the command line options have changed...  https://groups.google.com/g/chipyard/c/oTuVAmoJugU

[Øyvind Harboe]

I have tried to gather some information on the dontTouch() failures: I have tried to gather some information on the failures with MegaBoomConfig: https://github.com/llvm/circt/issues/6143