chiseltest failed on chisel 6.0

qwer trump (zsjj)

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Jan 30, 2024, 9:12:15 PMJan 30

to chisel-users

Hi all,

below is my test code, it can run well on chisel 3.6. but failed on chisel 6.0.

does anyone know the reason ?

-----------------------

12
13 class AXI4SlaveRAM(implicit p: Parameters) extends LazyModule {
14 val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
15 val axi_m_param = AXI4MasterParameters("myaximaster")
16 val axi_m_port = AXI4MasterPortParameters(Seq(axi_m_param))
17 val axi_master = AXI4MasterNode(Seq(axi_m_port))
18 val ios = InModuleBody(axi_master.makeIOs())
19
20 ram.node := AXI4Buffer() := axi_master
21
22 lazy val module = new Impl
23 class Impl extends LazyModuleImp(this) {
24 val io = ios.head
25 }
26 }
27
28 class AXI4RAMTest extends AnyFlatSpec with ChiselScalatestTester {
29 behavior of "AXI4RAM"
30
31 it should "perform axi rw operations correctly" in {
32 implicit val p = new BaseConfig
33 val axiram = LazyModule(new AXI4SlaveRAM())
34 test (axiram.module) { dut =>

-----------------------------------------------------------------

the error log is:

~~~~~~~~~~~

AXI4RAM
- should perform axi rw operations correctly *** FAILED ***
scala.NotImplementedError: TODO: convert SRAMAnnotation(ComponentName(mem,ModuleName(AXI4RAM,CircuitName(AXI4SlaveRAM))),8,mem,32,256,mem,8)
at chiseltest.simulator.ChiselBridge$.convert(ChiselBridge.scala:151)
at chiseltest.simulator.ChiselBridge$.$anonfun$annosToState$2(ChiselBridge.scala:93)
at scala.collection.immutable.List.flatMap(List.scala:293)
at scala.collection.immutable.List.flatMap(List.scala:79)
at chiseltest.simulator.ChiselBridge$.annosToState(ChiselBridge.scala:93)
at chiseltest.simulator.ChiselBridge$.elaborate(ChiselBridge.scala:73)
at chiseltest.simulator.Compiler$.elaborate(Compiler.scala:19)
at chiseltest.internal.BackendExecutive$.start(BackendExecutive.scala:23)
at chiseltest.defaults.package$.createDefaultTester(defaults.scala:25)
at chiseltest.ChiselScalatestTester$TestBuilder.apply(ChiselScalatestTester.scala:32)
...

~~~~~~~~~~~

Thanks for any help!!!!!

Kevin Laeufer

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Jan 31, 2024, 7:42:26 AMJan 31

to chisel...@googlegroups.com

This is a bug in chiseltest. It would be great if you could file an issue here: https://github.com/ucb-bar/chiseltest

Thanks!

- Kevin

On Jan 30, 2024, at 21:12, qwer trump (zsjj) <viv...@gmail.com> wrote:

Hi all,

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qwer trump (zsjj)

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Feb 3, 2024, 10:36:56 PMFeb 3

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Thanks! I will file an issue.

- qwer trump

Dmitry Belimov

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Feb 4, 2024, 1:55:49 AMFeb 4

to chisel...@googlegroups.com

Hi All,

Is it possible to transform Chisel code to C++ sources without
iverilator?

Why I ask this question?
We think to try to design functionality with Chisel and export as
Verilog for FPGA and as C++ for DSP.

C++ sources should be as library for working program not for
simulation.

Regards, Dmitrii.

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