bit order on asUInt

[Martin Schoeberl]

Hi all,

I am wondering why the mapping of a Vec to UInt is different from mapping a Bundle:

val vec = Wire(Vec(4, UInt(8.W)))
val word = vec.asUInt

The maps the first element to the lower bits.

class MyBundle extends Bundle {
  val a = UInt(8.W)
  val b = UInt(16.W)
}

val bundle = Wire(new MyBundle)
val word2 = bundle.asUInt

However, here the last field is mapped to the lower bits. Is there a deeper reason for the difference? Or did it “just happen”.

Cheers,

Martin