Absorb wire for IO blackbox connection

[Martoni]

Hello,

I have a problem with the last version of Gowin EDA synthesizer (1.9.8.03) as I explained on my GbHdmi issue project :

https://github.com/Martoni/GbHdmi/issues/3

I have to connect an lvds output buffer named TLVDS_OBUF on differential FPGA output.

To instanciate the buffer I wrote a blackbox. And I'm connecting the blackbox as it :

```scala
class GbHdmi(gowinDviTx: Boolean = true) extends Module
with GbConst with GbHdmiConst{
val io = IO(new Bundle {
//...
/* HDMI output signals */
val tmds = Output(new TMDSDiff())

//...

})

//...

val buffDiffRed = Module(new TLVDS_OBUF())
buffDiffRed.io.I := serdesRed.io.q
io.tmds.data(2).p := buffDiffRed.io.O

io.tmds.data(2).n := buffDiffRed.io.OB

```

This works and generate Verilog without problem but generate a verilog wire to connect module port :

```Verilog

//..

wire buffDiffRed_O;

//..

assign io_tmds_data_2_p = buffDiffRed_O; // wire connection

//...

TLVDS_OBUF buffDiffRed (

 .O(buffDiffRed_O),

 .OB(buffDiffRed_OB),

 .I(buffDiffRed_I) );

//..

endmodule

```

And gowin synthesizer doesn't like it and refuse to connect port through wire :

```

ERROR (CV0013) : Pin(buffDiffRed_O) of 'io_tmds_data_2_p'(TLVDS_OBUF) does not connect to port("/home/user/myapp/GbHdmi/TopGbHdmi.v":1115)

```

If I suppress this verilog wire by hand and connect io port directly it's work.

I'm sure that is a gowin synthesizer problem but is there a way to 'absorb' this wire and connect io module directly to the buffer with Chisel ?

Modifying Verilog generated code is a pain. It couldn't be a definitive solution.

Thanks

Fabien