Can I change the Verilog names of a Vec?

[Øyvind Harboe]

If I have:

val foo = Vec(5, UInt(2.W))

can I somehow set the name of each vector entry?

io_foo_1

is less readable than:

io_foo_bar

as I have to look up in the source how 1 translates to bar while reading the Verilog. Lots of context switching and inaccessible to those who only read the Verilog.

[Jack Koenig]

There isn't a way to set the names of Vec entries. If you want to set the names, why not just use a Bundle?

If they're all the same type, you can take advantage of multiple-declaration syntax in Scala:

class MyBundle extends Bundle {
  val a, b, c, d, e = UInt(8.W)
}

https://scastie.scala-lang.org/eh9ViOUgRGmAUCJySigTNQ

If you need more power than that, you can look at using a Record (https://www.chisel-lang.org/api/3.4.2/chisel3/Record.html). It's a power-user API so there unfortunately isn't documentation but it's like a Bundle except you implement elements and cloneType (rather than Chisel deriving them for you from the public vals)

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[Øyvind Harboe]

The Vec() in my case is used together with a Scala Enumeration.

Also, I assign sequences to the Vec(), creating  a bundle like you describe would break that and force me   to update the code everywhere if i add or remove from the enum.

So really I need the exact behavior of Vec() but to be able to use the enum name instead of the Vec() index in the Verilog.

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