Wrapping C++/Verilog code in chisel.

[Arka Maity]

Hi,
     Is it possible to wrap C++ code within a chisel module (like we do in bluespec)
Thanks and regards
Arka

[Jonathan Bachrach]

no, not at this time.  currently in chisel2.x, you can emit c++ and drive the simulation yourself from a C++ harness that you write yourself.  the c++ emulator header presents an api.  this is how they do it in the rocket chip generator.  finally, we are developing a framework for doing simulation with many different kinds of simulation elements which should help moving forward.  

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[Muzaffer Kal]

This is also of interest to me. I am in process of writing some dsp/decoding code which interfaces to some existing pcs in Verilog.

My initial thought was to generate C++ and interface that to the SystemVerilog simulator with DPI. Any other options at this point?

[Jonathan Bachrach]

no that's pretty much the option now.  we are working really hard this summer to come up with a much better simulation story.

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