Auto output-register creation

[Manili]

Hi all,

Is there a way to create a function which can create output-registers at compile time and assign them to outputs? As an example:

class MyOutputBundle extends Bundle {

    val a = Bool()

    val b = UInt(8.W)

}

class MyModule extends MultiIOModule {

    input = IO(Input(new Bundle { val en = Bool()}))

    output = IO(Output(new MyOutputBundle()))

    regsOutput = CreateOutputRegisters(output) //Here "CreateOutputRegisters" is what I'm talking about.

    when(input.en === true.B) {

        regsOutput.a := false.B

        regsOutput.b := 12.U

    }.otherwise {

        regsOutput.a := true.B

        regsOutput.b := 10.U

    }

}

Regards,

Manili

[waleed....@iiu.edu.pk]

You can do something like make a bundle of without flop and flop the comp bundle to assign to the output and make combinatorial hardware on the back of without flop bundle.

Hope this is helpful :)

import chisel3._

import chisel3.util._
import chisel3.experimental.DataMirror

class MyOutputBundle extends Bundle {
    val a = Bool()
    val b = UInt(8.W)
}
class MyModule extends MultiIOModule {

    val input = IO(Input(new Bundle {

      val en = Bool()
    }))

    val output = IO(Output(new MyOutputBundle()))
    
    val without_flop = Wire(new MyOutputBundle())
 
    output <> RegNext(without_flop)

    when(input.en === true.B) {
        without_flop.a := false.B
        without_flop.b := 12.U
    }.otherwise {
        without_flop.a := true.B
        without_flop.b := 10.U