Fwd: [eecs-announce] Talk by Scott Beamer (UCSC) at SLICE Lab on Wed., 9/25/24 at 11:05 A.M., Room 380 Soda

[Martin Schoeberl]

Dear all,

if you are in the Berkeley area this talk might interest you. Scott was involved in Chisel in the very beginning and is teaching now an agile hardware design course, which contains very inspirational open-source teaching material: https://classes.soe.ucsc.edu/cse228a/Winter24/

Cheers,

Martin

PS: I did not paste the Zoom link into this wide email list, as I do not have the right to do this. Maybe you can get it directly from Scott.

Begin forwarded message:

From: "SLICE Administration" (via eecs-announce Mailing List) <eecs-a...@lists.eecs.berkeley.edu>

Subject: [eecs-announce] Talk by Scott Beamer (UCSC) at SLICE Lab on Wed., 9/25/24 at 11:05 A.M., Room 380 Soda

Date: 23. September 2024 at 10:00:00 GMT-7

To: undisclosed-recipients:;

Reply-To: SLICE Administration <slice...@eecs.berkeley.edu>

Hi All,

SLICE Lab is welcoming Scott Beamer (UC Santa Cruz) this Wednesday, 9/25/24 at 11:05 a.m. 

in 380 Soda or via Zoom.

When: Wed., 9/25/24 at 11:05 a.m.

Where: 380 Soda or Zoom

Speaker: Scott Beamer, UC Santa Cuz

Title: Accelerating RTL Simulation with a Vertically-Integrated Approach

 

Abstract: Simulation is a critical tool for hardware design but its current slow speed often bottlenecks the entire design process. Simulation speed becomes even more crucial for agile and open-source hardware design methodologies, because the designers not only want to iterate on designs quicker, but they may also have less resources with which to simulate them.In this work, we survey our various techniques for accelerating hardware (RTL) simulation. We explore the challenge of efficiently detecting opportunities for reuse due to low activity factors, and we demonstrate streamlined techniques to profitably exploit them. We take advantage of the replication that is common in large designs to increase scalability. We parallelize simulation for multicore and achieve super-linear speedups. Throughout our work, we leverage insights about both the application workload and the host platform. Many of our innovations are enabled by novel graph partitioning algorithms or optimizations for the host processor. Our simulators outperform both leading open-source and industrial simulators, and we use performance counters to analyze our performance advantages.

 

Bio: Scott Beamer is an assistant professor of Computer Science & Engineering at the University of  California, Santa Cruz where he leads the Vertical Architectures, Memory, and Algorithms (VAMA) research group. His research interests include agile hardware design, high-performance graph processing, and computer architecture. His work has been recognized with an NSF CAREER Award, the Kaivalya Dixit Distinguished Dissertation Award from SPEC, best paper awards from the International Parallel & Distributed Processing Symposium (IPDPS) and the International Symposium on Workload Characterization (IISWC), and a distinguished paper award from International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). He earned all of his degrees (PhD, MS, BS) from UC Berkeley and was a postdoctoral scholar at Lawrence Berkeley National Laboratory.

 

----------------------------------------------------------------
You received this message via the eecs-announce mailing
list.  To unsubscribe, send mail to sy...@lists.eecs.berkeley.edu
with "unsubscribe eecs-announce" in the *subject* of the message.
Questions to eecs-annou...@lists.eecs.berkeley.edu.