Create verilog testbenches from Chisel tests

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Hi,

I have a question that you guys might know its answer. I already test my design by using Chisel's peek poke tester. However, I need to test by using other tools. Is there any way to create Verilog testbenches from the Peek Poke tester written in Chisel (scala). I wanna test and verify my testbench by using other tools which they won't support scala but support verilog testbenches.

Thanks in advance.