Chiseltest performance for representation of memories

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Warren Savage

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May 9, 2022, 3:44:32 PMMay 9
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I'm looking for anyone's experience in the comparative performance of Chiseltest+Verilator for simulating designs with a lot of memory.

I have a design that will never be fabricated but am playing with a number of highly parameterized architectures using wildly varying amounts of memory.  I want to evaluate these from simulation test cases.

I assumed that implementing it with Vec's of Reg would be pretty fast, but found when it gets to 3M flip-flops, it gets pretty slow and starts running out of memory.  I eventually want to evaluate up to 100-500M flip-flips, which will clearly break everything as written today.

I thought about trying the built-in Mem to see if that is faster.   Or just blackboxing a behavioral  Verilog model.  But before either, I thought I'd ask if anyone  had been here before.  

Any thoughts, recommendations?

Warren


Kevin Laeufer

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May 9, 2022, 3:48:31 PMMay 9
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Definitely use a built in amen whenever possible. That will simulate much faster than a Vec and also reduce the compile times and size of generated Verilog by a lot.
Essentially when something behaves like a memory, I.e. limited number of read and write ports for a single entry, you should use Mem. Vec mostly makes sense if you need parallel access of all elements.

Kevin

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On May 9, 2022, at 12:44, Warren Savage <warren...@rocksavage.tech> wrote:

I'm looking for anyone's experience in the comparative performance of Chiseltest+Verilator for simulating designs with a lot of memory.
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Warren Savage

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May 10, 2022, 7:30:00 PMMay 10
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Wow, you aren't kidding.  WAY faster!   Thanks Kevin.


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Subject: Re: Chiseltest performance for representation of memories
 
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Øyvind Harboe

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May 18, 2022, 9:29:11 PMMay 18
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What I did when I needed gigabytes of memory for a design, is that I implement the memory in C++ outside of Verilator. In my case it was easy to make the memory master interface available at the top level of the design.

If you have memories deep inside the design, then you *could* use BoringUtils to dependency inject the memory such that the memories are available at the top level of your design and that you can implement the memory in C++ outside of Verilator.

If your memory is implemented in C++, size doesn't matter w.r.t. performance beyond the time that it takes the CPU that runs Verilator to read and write to that memory.

Using BoringUtils on signals is straightforward. I've gotten it to work for interfaces and dependency inject like I describe above, but it is a bit finicky and outside the scope of what BoringUtils supports directly.



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