Chisel v3.6.0-RC1 has been released!

[Jack Koenig]

Howdy Chiselers,

I am very delighted to announce that we have released v3.6.0-RC1 of the various Chisel-related projects:

Chisel v3.6.0-RC1 - https://github.com/chipsalliance/chisel3/releases/tag/v3.6.0-RC1

ChiselTest v0.6.0-RC1 - https://github.com/ucb-bar/chiseltest/releases/tag/v0.6.0-RC1

Treadle and FIRRTL also have 1.6.0-RC1 releases but with relatively minor changes.

The 3.6 release is a big step for the future of Chisel as it is the transitionary release from the original Scala FIRRTL Compiler to the new LLVM MLIR-based FIRRTL Compiler. Please see the Chisel release notes linked above.

Please try out Chisel v3.6.0-RC1 to help us squash any bugs before the final v3.6.0 release!

~Jack on behalf of the Chisel development team

P.S. My usual Scastie template now using 3.6.0-RC1: https://scastie.scala-lang.org/2x4dtVkNS9SKq5v5qW5N5A

[Øyvind Harboe]

Various observations:

Tweaks required to make it build going from 3.5.6 to 3.6.0-RC1.

I had to remove chisel-circt from my build.sbt, built into 3.6.0, I suppose.

I get this error message:

object stage is not a member of package chisel3.util.circt

Deleting: 

import chisel3.util._

Fixes it.

Commenting out these lines:

object CIRCTHandover is not a member of package circt.stage

Some more cleanup needed:

class ChiselStage in package stage is deprecated (since Chisel 3.6): this feature will not be supported as part of the migration to the MLIR-based FIRRTL Compiler (MFC). For more information about this migration, please see the Chisel ROADMAP.md. Please switch to circt.stage.ChiselStage.

value DataMirror in package experimental is deprecated (since Chisel 3.6): This value has moved to chisel3.reflect

method apply in object forceName is deprecated (since Chisel 3.6): this feature will not be supported as part of the migration to the MLIR-based FIRRTL Compiler (MFC). For more information about this migration, please see the Chisel ROADMAP.md.

Since I have to comment out import chisel3.util._, to get circt.stage to work, I added import chisel3.util.log2Ceil explicitly.

If with these changes, it passes all tests, I'll try a P&R of my design and run it on the FPGA.

Note that I can't try LLVM CIRCT yet, I'm waiting for LLVM CIRCT 1.3x.0 to land a few bugfixes that I know are in the pipeline. In particular related to BoringUtils.

[Øyvind Harboe]

Worked in Quartus P&R and on FPGA.

Cheers,

[Jack Koenig]

Thank you as always for the bump (and bug!) reports Øyvind, they are extremely helpful. At a minimum, there are clearly some things to add to the "Migration from Chisel 3.5" page on the release notes :)

Cheers!

Jack

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