Vivado Synthesis Errors in Chisel generated verilog files

[Arka Maity]

Hi all,
          I have a Module, which instantiates a submodule, but the submodule connections are all only made depending upon a (Scala) Boolean flag. Consider the following example

class CE(useFPU: Boolean) extends Module {
 val fpu     = Module(new FPU1)
 val dummyfpu = Module(new dummyFPU)
 val datapath= Module(new dpath)

 if(useFPU == 1) {                                                      
        fpu.io.fetchIn  <> datapath.io.fpu.fetchIn                                                 
        fpu.io.intIn    <> datapath.io.fpu.intIn                                                   
        fpu.io.intOut   <> datapath.io.fpu.intOut                                                  
        fpu.io.dmemIn   <> datapath.io.fpu.dmemIn                                                  
        fpu.io.dmemOut  <> datapath.io.fpu.dmemOut                                                 
    } else {                                                                                       
        dummyfpu.io.fetchIn  <> datapath.io.fpu.fetchIn                                            
        dummyfpu.io.intIn    <> datapath.io.fpu.intIn                                              
        dummyfpu.io.intOut   <> datapath.io.fpu.intOut                                             
        dummyfpu.io.dmemIn   <> datapath.io.fpu.dmemIn                                             
        dummyfpu.io.dmemOut  <> datapath.io.fpu.dmemOut                                            
    }
}

The Generated Verilog File (with useFPU flag set to false) looks something like this.

module FPU1(input noc_clk, input reset,                                                            
    output io_fetchIn_ready,                                                                       
    input  io_fetchIn_valid,                                                                       
    input [31:0] io_fetchIn_bits,                                                                  
    output io_dmemIn_ready,                                                                        
    input  io_dmemIn_valid,                                                                        
    input [31:0] io_dmemIn_bits_data,                                                              
    input [4:0] io_dmemIn_bits_regId,                                                              
    output io_intIn_ready,                                                                         
    input  io_intIn_valid,                                                                         
    input [31:0] io_intIn_bits,                                                                    
    input  io_dmemOut_ready,                                                                       
    output io_dmemOut_valid,                                                                       
    output[31:0] io_dmemOut_bits,                                                                  
    input  io_intOut_ready,                                                                        
    output io_intOut_valid,                                                                        
    output[31:0] io_intOut_bits_data,                                                              
    output[4:0] io_intOut_bits_regId                                                               
);

This Module however also gets instantiated as

FPU1 fpu(.noc_clk(noc_clk), .reset(reset),                                               
       //.io_fetchIn_ready(  )                                                                     
       //.io_fetchIn_valid(  )                                                                     
       //.io_fetchIn_bits(  )                                                                      
       //.io_dmemIn_ready(  )                                                                      
       //.io_dmemIn_valid(  )                                                                      
       //.io_dmemIn_bits_data(  )                                                                  
       //.io_dmemIn_bits_regId(  )                                                                 
       //.io_intIn_ready(  )                                                                       
       //.io_intIn_valid(  )                                                                       
       //.io_intIn_bits(  )                                                                        
       //.io_dmemOut_ready(  )                                                                     
       //.io_dmemOut_valid(  )                                                                     
       //.io_dmemOut_bits(  )                                                                      
       //.io_intOut_ready(  )                                                                      
       //.io_intOut_valid(  )                                                                      
       //.io_intOut_bits_data(  )                                                                  
       //.io_intOut_bits_regId(  )                                                                 
  );

The way this FPU1 is intantiated in verilog is not accepted by vivado synthesis because of presence of "," character in the end of the line, FPU1 fpu(.noc_clk(noc_clk), .reset(reset),
I manually edit the generated verilog files, as of now. Is it a chisel bug or do other synthesis tools accept this verilog?

I use the following flag to compile my chisel code
Array("--backend", "fpga", "--targetDir", "rtl", "--genHarness")

Also is it possible to conditionally instantiate a module in the first place ?


 

[Schuyler Eldridge]

You can get an example of conditional Module instantiation and conditional connections in how the the existing rocket FPU is instantiated and wired up. I think the Chisel code used here should work for you: https://github.com/ucb-bar/rocket/blob/master/src/main/scala/tile.scala#L61

This is only wiring everything up if the FPU actually exists (i.e., foreach over None won't do anything) and should work for your usage case.