Reversing reset polarity

[Oguz Meteer]

Since I'm very new to Chisel, I started out making a very simple counter to blink some leds on my Lattice iCEstick. I found that the iCEstick uses a inverted reset signal, so I have to manually invert the reset signal in the generated verilog. I saw that the RocketTile class (and its parent class Tile) and this example supply a Bool value to the _reset signal in Module, which apparently can be used to invert the reset signal polarity.

However, I cannot get that to work as I get an error. Here is the code:

import Chisel._

class Blink( swidth: Int, rstPol: Bool = null ) extends Module( _reset = rstPol ) {
  val io = new Bundle {
    val led = UInt( OUTPUT, 5 )
  }
 
  val counter = Reg( init = UInt( 0, width = swidth ) )
 
  counter := counter + UInt( 1 )
 
  io.led := counter( swidth - 1, swidth - 5 )
}

object BlinkMain {
  def main( args: Array[ String ] ): Unit = {
    chiselMain( Array( "--backend", "v", "--targetDir", "verilog" ),
      () => Module( new Blink( 27, Bool( false ) ) )
    )
  }
}

This gives me the error:

[error] Blink.scala:18: < /*??*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) > doesn't have its component, yet. in class BlinkMain$$anonfun$main$1$$anonfun$apply$1
[error] (run-main-9) Chisel.ChiselException: < /*??*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) > doesn't have its component, yet.
Chisel.ChiselException: < /*??*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) > doesn't have its component, yet.
 at BlinkMain$$anonfun$main$1$$anonfun$apply$1.apply(Blink.scala:18)
[trace] Stack trace suppressed: run last compile:run for the full output.
java.lang.RuntimeException: Nonzero exit code: 1
 at scala.sys.package$.error(package.scala:27)
[trace] Stack trace suppressed: run last compile:run for the full output.
[error] (compile:run) Nonzero exit code: 1

When I don't supply a Bool parameter, then I get no error since the default value of null is used which is valid. I've also tried changing the null to Bool( false ), and _reset = Bool( false ), but I get the same error.

Like I said, I'm very new to Chisel and also Scala, but as far as I can tell, this should work.

I'm using Scala 2.11.7 and Chisel 2.2.33 (latest.release).

[Martin Schoeberl]

Here is an (maybe too elaborated) example how to do the reset inversion:

https://github.com/schoeberl/chisel-examples/blob/master/examples/src/main/scala/simple/KnightRider.scala

Ignore ResetGem, but just see how an input button is inverted and synchronized with the clock through two registers and than passed to a component.

Cheers,

Martin

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[Oguz Meteer]

Hi Martin,

If you check out the link (this example) in my original post, you will see that it is the same link as the one you provided :)

I did just fixed the problem, and now I know what I did wrong. _reset expects a Bool INPUT whereas I provided a Bool( false ) which is an OUTPUT. And indeed, just as the example shows, you need a Bool input signal (connected to a pin). This is what I came up with:

import Chisel._

class Blink( swidth: Int, rst: Bool = null ) extends Module( _reset = rst ) {

  val io = new Bundle {
    val led = UInt( OUTPUT, 5 )
  }

  val counter = Reg( init = UInt( 0, width = swidth ) )

  counter := counter + UInt( 1 )

  io.led := counter( swidth - 1, swidth - 5 )
}

class Top extends Module {

  val io = new Bundle {
    val led  = UInt( OUTPUT, 5 )

    val rstn = Bool( INPUT )
  }

  val rst   = Reg( next = Reg( next = !io.rstn ) )
  val blink = Module( new Blink( 27, rst ) )

  blink.io.led <> io.led

}

object BlinkMain {
  def main( args: Array[ String ] ): Unit = {
    chiselMain( Array( "--backend", "v", "--targetDir", "verilog" ),

      () => Module( new Top() )
    )
  }
}

Thanks for the input!

Cheers,

Oguz