I've discovered that when I get error messages about uninferred widths, it can be because that input has not been assigned yet.
It would of course be much less confusing if the error message was about the unassigne input...
[info] firrtl.passes.PassExceptions: firrtl.passes.CheckWidths$UninferredWidth: : Uninferred width for target below. (Did you forget to assign to it?)
[info] circuit FooTestBench:
[info] └── module VecAccess:
[info] └── element