Chisel Generated AXI4 limitations

[derik Veliz]

Hi, I'm using a formal tool to look over a DDR4 AXI4 interface that is generated by Chisel code. I'm getting violations with the WSTRB and 4K boundary limits in this interface and a few other AXI4 interfaces. I know Chisel doesn't generate a fully implemented AXI4 so I was wondering if these type of violations were to be expected? Thank you.

[Kevin Laeufer]

Hi Derik,

Sounds like there might be a bug in the AXI RTL you are using.
I would recommend filing an issue with the RTL authors. If you attach
some of the failing traces to the issue, that might also be helpful.

Regards,
Kevin

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