VecInit

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Martin Schoeberl

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Jul 26, 2022, 9:49:28 AMJul 26
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Dear all,

When I use a Vec as a combinational circuit (a mux) I need to wrap it into a Wire. When using VecInit as combinational circuit with default values, I can wrap it into a WireDefault (not into a Wire). However, VecInit also works without the WireDefault:

val defVec = VecInit(1.U(3.W), 2.U, 3.U)
when (cond) {
defVec(0) := 4.U
defVec(1) := 5.U
defVec(2) := 6.U
}
val vecOut = defVec(sel)

is the same as

val defVec = WireDefault(VecInit(1.U(3.W), 2.U, 3.U))
when (cond) {
defVec(0) := 4.U
defVec(1) := 5.U
defVec(2) := 6.U
}
val vecOut = defVec(sel)

A plain Vec needs to be wrapped into a Wire.

This feels a bit inconsistent. What is the preferred style? Probably the one without WireDefault as it is shorter. I have also not found a single usage of WireDefault/Init(VecInit... in the Chisel test code.

Using it as a Reg with initialization needs the RegInit wrapping.

Currently I am writing about all this in Chapter 2 of the Chisel book. Maybe this is way too early. But I don't want to start another Chapter later just to repeat Vecs. Any opinion on how to structure this?

BTW, if you want to follow the book changes (and give me feedback ;-) do a git clone [1]. A simple "make" will build the whole book (needs Latex installed).

Cheers,
Martin

[1] https://github.com/schoeberl/chisel-book
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