New to Chisel

[foo leng leong]

Hi All,

I am new to Chisel and Scala. 

Some background information, I am well versed in Verilog, would like to explore using Chisel

I do not have any prior knowledge or experience with any programming language like C++ or Java or Scala

How should I start? Which language should I start familiarizing myself to kick start 

Also, does it make sense for me to use Chisel anew rather than sticking to verilog, which I am already very experienced in

Thanks alot in advance! 

[Mohammad Hossein Askari Hemmat]

Hi foo leng,

I am also new to Chisel and Scala (although I have been working with C++ for couple of years now). The OOP part might be a bit confusing for you so I suggest 

you to take some MOOC. What I found useful was  Functional Programming Principles in Scala in Coursera. Again, it might a bit hard to catch on with some concepts.

If you find that hard to follow, I suggest you to watch Introduction to the Art of Programming using Scala on YouTube which was prepared by Mark Lewis. He starts from very

basic concepts and Unlike the Coursera course, I don't see any pre-requisite for this series. After that, I would recommend to start with Chisel tutorials. I found them sufficient 

to start. But you absolutely need to look at the codes in Risc-V repo. This will help to understand nuts and bolts of Chisel. 

If you think you are already familiar with concepts (basic and advance) in Verilog, I don't see anyreason to not try a new hdl.

Best,

Hossein

[Edmond Cote]

I think you're in for a rough learning curve given that you have no experience with any programming languages.

I originally tried Chisel ~2 yrs ago without knowing much/any about Scala (or functional programming).  Last year, I audited some of the online Scala classes (.. and wish I had the time to work though them) and found the Chisel and it's syntax (largely Scala and DSL additions) much more manageable.

-Ed

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[foo leng leong]

Hi Ed,

Indeed, I agree with you. I have very basic programming knowledge in C, thats about it.

I am actually a ASIC designer who wants to try out Chisel. 

For someone like myself who is already very familiar with Verilog, does it make sense to try Chisel?

I find it weird because eventually I will still end up with a verilog code which I will use to synthesis and simulate, more like double job for me.

Apparently Chisel does not save much in silicon area, but more for simulation speed, is that right? I am sorry for the barrage of questions as I am very new to this

Thanks again

Foo Leng

[foo leng leong]

Hi Hossein,

Thanks for the input. Firstly I will need to apologize about my lack of knowledge in programming languages, can you tell me what is OOP and MOOC?

Secondly, I will also like to ask you the same question which I asked Ed, whats the main advantage of Chisel other than faster simulation speed.

Also, is there some logic equivalence checker that I can use between verilog and my Chisel code?

Thanks

Foo Leng

[Kamyar Mohajerani]

Hi,

Well Chisel does NOT save you any simulation time. For larger designs you most probably end up using a Veirlog simulation backend (Verilator or VCS) where the Verilog generation overhead time is also added. What you will end up saving is the "design time". It's much easier to develop fully parameterized and reusable component "generators" and reuse them in your future designs. Designs in chisel much cleaner and you end up with fewer lines of code which is usually more easier to understand or modify. I also find design verification much easier and more flexible in Chisel. And then there's the load of advanced stuff that you can do using the power of Scala and Chisel3's FIRRTL passes.

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[Mohammad Hossein Askari Hemmat]

OOP stands for Object Oriented Programming (take a look at this wiki page) and MOOC stands for Massive Open Online Course where you can learn a wide range of subjects from top universities. 

For your second question, I think Kamyar correctly pointed out the benefits of using Chisel.

The process of transforming Chisel to Verilog is done by firrtl in which the transformation is verified you can have look to this repo: https://github.com/ucb-bar/firrtl

[Schuyler Eldridge]

Chisel will save you enormously because of both:

  * Object oriented features

  * Functional programming

System Verilog has great OOP features, but, last I checked, these are all strictly simulation only for most ASIC/FPGA workflows. As a consequence, I've always had two flavors of Verilog writing: OOP testbenches and painfully imperative Verilog designs in incredibly rigid design patterns that the synthesis tools like. With Chisel (or some other language that's generating a hardware description) you're completely free to design how you want at some (assumed) cost to the efficiency of the Verilog generated. The assumption is that this design trade-off is worth it. You gain hardware designer speed and immense amounts of reuse.

On the functional side, you can be ridiculously terse in the types of complex structures you want to describe which should improve designer speed while resulting in clearer more understandable code. Nonetheless, this can be difficult for pure hardware engineers initially , e.g., a portion of the CSR file of rocket:

// Description of the CSRs

object CSRs {

  val fflags = 0x1

  val frm = 0x2

  val fcsr = 0x3
  // ...
}

// A mapping of the CSR Ints above to some underlying registers
val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](

    CSRs.tselect -> reg_tselect,

    CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt,
    // ...
}

// A function that converts read_mapping to a list of boolean checks on address matches

val decoded_addr = read_mapping map { case (k, v) => k -> (io.rw.addr === k) }

// Dereference the first register that matches
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)

Handling the above complexity in Verilog is an exercise in patience. In Chisel it's just an understanding of OOP, functional programming, and Scala. However, coming from C this looks unintelligible.

The problem is that most hardware designers don't have this OOP/functional exposure (or I certainly didn't!). The MOOCs do help. After all the CS nonsense, the next thing is to just get comfortable with the Chisel codebase. The tutorials, cheatsheets, and examples are all good, however, I've found it to be much more efficient to just look at the API spec (https://chisel.eecs.berkeley.edu/api/index.html#package). Alternatively, install and use ctags so that you can do the API browsing on the command line. There is _a lot_ of interesting features which you just don't come across unless you have access to the API. If you have some module that you want to implement, look at something roughly equivalent in rocket-chip to see how Berkeley/SiFive went about it. They know what they're doing and reading good code helps. Also, Scala has a read-eval-print-loop (REPL) like python. Just install Scala and run it from the command line. That's proven invaluable for playing with some of the more alien functional program stuff (`map`, `zip`, `zipWithIndex`, `flatMap`, etc.).

Alternatively, it's relatively easy to do a direct translation of Verilog into Chisel as an initial step and then start using more and more features as your comfort level increases. This was the original path that I did and I've been pushing others down it as well.

I think you can avoid the LEC check of Chisel -> Verilog. Everything that you simulate is always Verilog (or that's how it works with the current rocket-chip approach). That's not the case with Chisel testers. So, if you do your functional verification in Verilog you then only have to worry about LEC checks during the ASIC/FPGA flow.

[foo leng leong]

Hi Kamyar,

Thanks for your reply, I inferred the savings in simulation from a UC Berkeley paper which I come across.

I will need a few days to read and digest all the information kindly provided to me by everyone here before I can comment on anything else

Thanks again

Foo Leng

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[foo leng leong]

Hi Hossein,

Thanks for the links, will read through them carefully

Also looking at FIRRTL notes and syntax

Thanks again

Foo Leng

[foo leng leong]

Hi Eldridge,

Thank you for your very detailed explanation. 

So it seems like most simulation will still be in Verilog, if so, can i say that the final functional signoff will still be from Verilog simulation.

Chisel simulation will just mainly be for functional checks during coding.

Indeed, I plan to start by converting some of my current verilog codes to Chisel first, but since I am a novice, I do not know how to start doing so. Is there any tools which I can use? ( like FIRRTL equivalent, or maybe firrtl is both ways?)

Thanks again for all the help

Foo Leng

[Schuyler Eldridge]

Hi Foo Leng,

Unfortunately there's no clean way of going from Verilog/VHDL -> Chisel in an automated way (though I'm not sure that you would want to do that). However, you can do a rough manual conversion which isn't too bad. Anecdotally, this is how I started and how I've seen others from a pure hardware design background start. 

If you have unit tests for your Verilog modules, you could convert them to Chisel, generate Verilog from those, then verify that they still pass your unit tests. This is somewhat pedantic, but it would guarantee correctness.

In terms of doing a flat translation, the basic Verilog constructs have the following Chisel equivalents:

* `always @(condition)`, `always_comb`, `always_ff` -> `when (condition)`

* `case(signal)` -> `switch(signal)`

* `reg[7:0] x` -> `Reg(UInt(8.W))`

* `wire[2:0] y` -> `Wire(UInt(3.W))`

System Verilog structs/interfaces are roughly analogous to `Bundle`. 

Chisel Bundles and Modules can take parameters which, at a first pass, are a superset of Verilog `#` parameters.

I'd suggest to just start converting and you'll get the hang of it. 

Schuyler

[Mohammad Hossein Askari Hemmat]

I also found the chisel-coding-style very useful. Once you felt more comfortable with the syntax, you may want to look at this repo.