verilog output with Chisel v5.1.0

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chiselStudent

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Jan 23, 2024, 9:55:25 PMJan 23
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I am using the chisel-template gcd module and see that I can generate a system verilog file. using: 
object GCDMain extends App {
ChiselStage.emitSystemVerilog(
new GCD
)
}

But I was hoping there was a flag I could set to change it to verilog output? I saw that I can change the FirtoolOption, but not the CIRCTTargetAnnotation? 

Thanks for any help.
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