Chisel 3.6

[Martin Schoeberl]

Hi all,

as I read in the release notes, Chisel 3.6 shall be the version for a transition from the Scala based compiler to the MLIR compiler. How do I switch between those two backends in 3.6? When just running 3.6 it looks like the Verilog code generated is similar to the code generated from the Scala backend, not like the code generated from Chisel 5.0.

Cheers,
Martin

[Schuyler Eldridge]

Chisel 3.6 has two different "ChiselStage"s that you can use:

- `chisel3.stage.ChiselStage` class/object uses the Scala-based FIRRTL Compiler (SFC). This is marked deprecated in 3.6.

- `circt.stage.ChiselStage` class/object uses the MLIR-based FIRRTL Compiler (MFC)

Let me know if that works for you.

Schuyler

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[Martin Schoeberl]

I got the SFC running, but get a compile error when trying MFC:

[error] /Users/martin/source/chisel-empty/src/main/scala/empty/Add.scala:31:9: object stage is not a member of package chisel3.util.circt

[error]   circt.stage.ChiselStage.emitVerilog(new Add())

[error]         ^

[error] one error found

Martin

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[Schuyler Eldridge]

There's two "circt" packages. One is under the top level. The other is under chisel3.util. The problem is that code is doing a wildcard import of chisel3.util._ which will then cause the latter to be used when you want the former.

Either change the import to not be a wildcard or explicitly use/import "_root_.circt.stge.ChiselStage".

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[Martin Schoeberl]

Dropped the import, but both versions gave me errors:

circt.stage.ChiselStage.emitVerilog(new Add())

_root_.circt.stage.ChiselStage.emitVerilog(new Add())

[error] /Users/martin/source/chisel-empty/src/main/scala/empty/Add.scala:30:27: value emitVerilog is not a member of object circt.stage.ChiselStage

[error]   circt.stage.ChiselStage.emitVerilog(new Add())

[error] /Users/martin/source/chisel-empty/src/main/scala/empty/Add.scala:30:34: value emitVerilog is not a member of object circt.stage.ChiselStage

[error]   _root_.circt.stage.ChiselStage.emitVerilog(new Add())

However, it is not so important as I simply can switch in build.sbt between Chisel versions (3.6 and 5).

Martin

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[Schuyler Eldridge]

Try emitSystemVerilog for the circt variant.

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[Martin Schoeberl]

OK, that compiled.

Thanks,

Martin

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