Case statements in Verilog

[Øyvind Harboe]

The lack of case-statements in the Verilog generated by Chisel is one of the things that causes the most angst about the Verilog generated by Chisel.

If I didn't have to have the conversation over and over again that the Verilog generated by Chisel for these cases reduces to the same RTL in synthesis, it would free up time and bandwidth to talk about other aspects of Chisel.

Is there a reason why Chisel shouldn't generate case statements for a MuxLookup()?

[Kevin Laeufer]

Hi Øyvind,

I believe it is fair to say that the reason why Chisel does not
currently generate case statements in Verilog is that it would be quite
a bit of work to implement with the way the compiler is currently
structured.

If you would like to make the case for having this feature, it would
definitely help if you could create an issue in which you show:
- a Chisel design that uses a MuxLookup
- the generated Verilog
- the generated Verilog with the MuxLookup manually implemented as a
case statement
- the QoR difference between the two equivalent designs
- instructions on how to reproduce your measurements

I cannot promise you that anyone will immediately pick this up and start
working on it. But having some hard data on QoR improvements would make
a good case for looking at this in the future. And, if it turns out that
there aren't any QoR differences, we will have a good experiment to
point people to in case they are afraid of the Chisel generated Verilog
being inferior.

Regards,
Kevin

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[Øyvind Harboe]

Makes sense.

My argument is not that this would increase QoR, but that Chisel generating case statements would reduce FUD w.r.t. generated Verilog from Chisel, because the Verilog generated would be much closer to what Verilog coders are used to writing themselves by hand.

How could I give data on improved QoR?

Commercial tools are under NDA, so publishing results is at best a pain.

What would be taken as authoritative evidence?

I could do a P&R using OpenROAD (Yosys, effectively) or I could use Quartus?

I have Chisel code where the QoR is higher, but that code is under NDA. I'd have to try to create a smaller example, but I fear the effects would not be evident in a smaller example.

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Øyvind Harboe
+4791786146

[Schuyler Eldridge]

> On Apr 6, 2021, at 01:33, Øyvind Harboe <oyv...@harboe.org> wrote:
>
> My argument is not that this would increase QoR, but that Chisel generating case statements would reduce FUD w.r.t. generated Verilog from Chisel, because the Verilog generated would be much closer to what Verilog coders are used to writing themselves by hand.

I agree. There's no reason to _not_ emit case statements. Having a QOR justification isn't necessary.

> On Apr 6, 2021, at 01:33, Øyvind Harboe <oyv...@harboe.org> wrote:
>
> How could I give data on improved QoR?
>
> Commercial tools are under NDA, so publishing results is at best a pain.
>
> What would be taken as authoritative evidence?
>
> I could do a P&R using OpenROAD (Yosys, effectively) or I could use Quartus?
>
> I have Chisel code where the QoR is higher, but that code is under NDA. I'd have to try to create a smaller example, but I fear the effects would not be evident in a smaller example.

I recall Yosys generating poor results for Verilog that doesn't use case statements as opposed to long if/else if/else trees. Most commercial tools won't have these issues.

I opened an issue about this (https://github.com/chipsalliance/chisel3/issues/1198) and got one commit into a solution (https://github.com/chipsalliance/chisel3/issues/1198) before I ran out of steam.

This may be easy enough for somebody to finish and get a decent result for obvious things like `MuxLookup`. The longer-term issue is that the Scala FIRRTL Compiler and Chisel create mix trees for high level constructs like `MuxLookup`. High level information is destroyed and has to be reconstructed via heuristics. (This information could be preserved via annotations, but that's not a great fit.). IR nodes for case/switch is the best fit, but an enormous FIRRTL IR expansion.

FWIW, this is one of the planned features of an extremely experimental Scala FIRRTL Compiler replacement using MLIR (https://github.com/llvm/circt). This already has a representation of `case`/`casez` in a SystemVerilog dialect and there's planned work to pattern match into this (See: https://github.com/llvm/circt/issues/675). Having infrastructure that lets multiple dialects coexist (e.g., FIRRTL IR and SystemVerilog) makes it a lot easier.

[Øyvind Harboe]

Looks like this is well in hand...  It is a matter of resources....

Thanks for the clarifications!

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