Difference between 3-stage and 5-stage RISC-V Sodor architecture

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sallo

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Aug 31, 2016, 5:00:42 AM8/31/16

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Hi, I just came across the Risc-V architecture and wonder what the difference is between the 3-stage and the 5-stage pipeline other than the depth. Thanks.

Christopher Celio

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Aug 31, 2016, 4:38:11 PM8/31/16

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The Sodor 3-stage is attached to a sequential memory scratchpad, while all of the other cores (including the 5-stage) talk to asynchronous memory.